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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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staging: comedi: s626: rename private data 'base_addr' variable
The base_address variable in the private data is the ioremap'ed PCI bar 0 resource. For aesthetic reasons, and to shorten some of the lines, rename this variable to 'mmio'. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
be008602e6
commit
7d856da216
@ -80,7 +80,7 @@ INSN_CONFIG instructions:
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#define PCI_SUBDEVICE_ID_S626 0x0272
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struct s626_private {
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void __iomem *base_addr;
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void __iomem *mmio;
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uint8_t ai_cmd_running; /* ai_cmd is running */
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uint8_t ai_continous; /* continous acquisition */
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int ai_sample_count; /* number of samples to acquire */
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@ -147,7 +147,7 @@ static void s626_mc_enable(struct comedi_device *dev,
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struct s626_private *devpriv = dev->private;
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unsigned int val = (cmd << 16) | cmd;
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writel(val, devpriv->base_addr + reg);
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writel(val, devpriv->mmio + reg);
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}
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static void s626_mc_disable(struct comedi_device *dev,
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@ -155,7 +155,7 @@ static void s626_mc_disable(struct comedi_device *dev,
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{
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struct s626_private *devpriv = dev->private;
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writel(cmd << 16 , devpriv->base_addr + reg);
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writel(cmd << 16 , devpriv->mmio + reg);
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}
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static bool s626_mc_test(struct comedi_device *dev,
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@ -164,7 +164,7 @@ static bool s626_mc_test(struct comedi_device *dev,
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struct s626_private *devpriv = dev->private;
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unsigned int val;
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val = readl(devpriv->base_addr + reg);
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val = readl(devpriv->mmio + reg);
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return (val & cmd) ? true : false;
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}
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@ -203,7 +203,7 @@ static void DEBItransfer(struct comedi_device *dev)
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;
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/* Wait until DEBI transfer is done */
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while (readl(devpriv->base_addr + P_PSR) & PSR_DEBI_S)
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while (readl(devpriv->mmio + P_PSR) & PSR_DEBI_S)
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;
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}
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@ -214,12 +214,12 @@ static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
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struct s626_private *devpriv = dev->private;
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/* Set up DEBI control register value in shadow RAM */
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
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/* Execute the DEBI transfer. */
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DEBItransfer(dev);
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return readl(devpriv->base_addr + P_DEBIAD);
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return readl(devpriv->mmio + P_DEBIAD);
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}
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/* Write a value to a gate array register. */
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@ -228,8 +228,8 @@ static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
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struct s626_private *devpriv = dev->private;
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/* Set up DEBI control register value in shadow RAM */
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writel(DEBI_CMD_WRWORD | addr, devpriv->base_addr + P_DEBICMD);
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writel(wdata, devpriv->base_addr + P_DEBIAD);
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writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
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writel(wdata, devpriv->mmio + P_DEBIAD);
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/* Execute the DEBI transfer. */
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DEBItransfer(dev);
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@ -245,14 +245,14 @@ static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
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struct s626_private *devpriv = dev->private;
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unsigned int val;
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
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DEBItransfer(dev);
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writel(DEBI_CMD_WRWORD | addr, devpriv->base_addr + P_DEBICMD);
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val = readl(devpriv->base_addr + P_DEBIAD);
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writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
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val = readl(devpriv->mmio + P_DEBIAD);
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val &= mask;
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val |= wdata;
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writel(val, devpriv->base_addr + P_DEBIAD);
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writel(val, devpriv->mmio + P_DEBIAD);
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DEBItransfer(dev);
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}
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@ -264,7 +264,7 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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unsigned int ctrl;
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/* Write I2C command to I2C Transfer Control shadow register */
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writel(val, devpriv->base_addr + P_I2CCTRL);
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writel(val, devpriv->mmio + P_I2CCTRL);
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/*
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* Upload I2C shadow registers into working registers and
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@ -276,7 +276,7 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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/* Wait until I2C bus transfer is finished or an error occurs */
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do {
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ctrl = readl(devpriv->base_addr + P_I2CCTRL);
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ctrl = readl(devpriv->mmio + P_I2CCTRL);
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} while ((ctrl & (I2C_BUSY | I2C_ERR)) == I2C_BUSY);
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/* Return non-zero if I2C error occurred */
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@ -315,7 +315,7 @@ static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
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return 0;
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}
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return (readl(devpriv->base_addr + P_I2CCTRL) >> 16) & 0xff;
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return (readl(devpriv->mmio + P_I2CCTRL) >> 16) & 0xff;
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}
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/* *********** DAC FUNCTIONS *********** */
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@ -355,7 +355,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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/* Copy DAC setpoint value to DAC's output DMA buffer. */
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/* writel(val, devpriv->base_addr + (uint32_t)devpriv->pDacWBuf); */
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/* writel(val, devpriv->mmio + (uint32_t)devpriv->pDacWBuf); */
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*devpriv->pDacWBuf = val;
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/*
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@ -373,7 +373,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* other FIFO underflow/overflow flags). When set, this flag
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* will indicate that we have emerged from slot 0.
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*/
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writel(ISR_AFOU, devpriv->base_addr + P_ISR);
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writel(ISR_AFOU, devpriv->mmio + P_ISR);
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/* Wait for the DMA transfer to finish so that there will be data
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* available in the FIFO when time slot 1 tries to transfer a DWORD
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@ -381,7 +381,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* Done by polling the DMAC enable flag; this flag is automatically
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* cleared when the transfer has finished.
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*/
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while (readl(devpriv->base_addr + P_MC1) & MC1_A2OUT)
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while (readl(devpriv->mmio + P_MC1) & MC1_A2OUT)
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;
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/* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
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@ -391,7 +391,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
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* detection.
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*/
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writel(XSD2 | RSD3 | SIB_A2, devpriv->base_addr + VECTPORT(0));
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writel(XSD2 | RSD3 | SIB_A2, devpriv->mmio + VECTPORT(0));
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/* Wait for slot 1 to execute to ensure that the Packet will be
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* transmitted. This is detected by polling the Audio2 output FIFO
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@ -399,7 +399,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* finished transferring the DAC's data DWORD from the output FIFO
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* to the output buffer register.
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*/
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while (!(readl(devpriv->base_addr + P_SSR) & SSR_AF2_OUT))
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while (!(readl(devpriv->mmio + P_SSR) & SSR_AF2_OUT))
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;
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/* Set up to trap execution at slot 0 when the TSL sequencer cycles
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@ -409,7 +409,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* buffer register.
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*/
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writel(XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS,
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devpriv->base_addr + VECTPORT(0));
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devpriv->mmio + VECTPORT(0));
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/* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
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@ -430,14 +430,14 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
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* the TSL has not yet finished executing slot 5 ...
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*/
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if (readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000) {
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if (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000) {
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/* The trap was set on time and we are still executing somewhere
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* in slots 2-5, so we now wait for slot 0 to execute and trap
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* TSL execution. This is detected when FB_BUFFER2 MSB changes
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* from 0xFF to 0x00, which slot 0 causes to happen by shifting
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* out/in on SD2 the 0x00 that is always referenced by slot 5.
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*/
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while (readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000)
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while (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000)
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;
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}
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/* Either (1) we were too late setting the slot 0 trap; the TSL
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@ -448,13 +448,13 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* In order to do this, we reprogram slot 0 so that it will shift in
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* SD3, which is driven only by a pull-up resistor.
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*/
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writel(RSD3 | SIB_A2 | EOS, devpriv->base_addr + VECTPORT(0));
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writel(RSD3 | SIB_A2 | EOS, devpriv->mmio + VECTPORT(0));
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/* Wait for slot 0 to execute, at which time the TSL is setup for
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* the next DAC write. This is detected when FB_BUFFER2 MSB changes
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* from 0x00 to 0xFF.
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*/
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while (!(readl(devpriv->base_addr + P_FB_BUFFER2) & 0xff000000))
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while (!(readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000))
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;
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}
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@ -491,13 +491,13 @@ static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
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/* Choose DAC chip select to be asserted */
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WSImage = (chan & 2) ? WS1 : WS2;
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/* Slot 2: Transmit high data byte to target DAC */
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writel(XSD2 | XFIFO_1 | WSImage, devpriv->base_addr + VECTPORT(2));
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writel(XSD2 | XFIFO_1 | WSImage, devpriv->mmio + VECTPORT(2));
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/* Slot 3: Transmit low data byte to target DAC */
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writel(XSD2 | XFIFO_0 | WSImage, devpriv->base_addr + VECTPORT(3));
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writel(XSD2 | XFIFO_0 | WSImage, devpriv->mmio + VECTPORT(3));
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/* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
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writel(XSD2 | XFIFO_3 | WS3, devpriv->base_addr + VECTPORT(4));
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writel(XSD2 | XFIFO_3 | WS3, devpriv->mmio + VECTPORT(4));
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/* Slot 5: running after writing target DAC's low data byte */
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writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->base_addr + VECTPORT(5));
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writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->mmio + VECTPORT(5));
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/* Construct and transmit target DAC's serial packet:
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* ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
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@ -534,13 +534,13 @@ static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
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*/
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/* Slot 2: Send high uint8_t to target TrimDac */
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writel(XSD2 | XFIFO_1 | WS3, devpriv->base_addr + VECTPORT(2));
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writel(XSD2 | XFIFO_1 | WS3, devpriv->mmio + VECTPORT(2));
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/* Slot 3: Send low uint8_t to target TrimDac */
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writel(XSD2 | XFIFO_0 | WS3, devpriv->base_addr + VECTPORT(3));
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writel(XSD2 | XFIFO_0 | WS3, devpriv->mmio + VECTPORT(3));
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/* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
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writel(XSD2 | XFIFO_3 | WS1, devpriv->base_addr + VECTPORT(4));
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writel(XSD2 | XFIFO_3 | WS1, devpriv->mmio + VECTPORT(4));
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/* Slot 5: Send NOP low uint8_t to DAC0 */
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writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->base_addr + VECTPORT(5));
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writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->mmio + VECTPORT(5));
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/* Construct and transmit target DAC's serial packet:
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* ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
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@ -885,16 +885,16 @@ static irqreturn_t s626_irq_handler(int irq, void *d)
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spin_lock_irqsave(&dev->spinlock, flags);
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/* save interrupt enable register state */
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irqstatus = readl(devpriv->base_addr + P_IER);
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irqstatus = readl(devpriv->mmio + P_IER);
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/* read interrupt type */
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irqtype = readl(devpriv->base_addr + P_ISR);
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irqtype = readl(devpriv->mmio + P_ISR);
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/* disable master interrupt */
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writel(0, devpriv->base_addr + P_IER);
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writel(0, devpriv->mmio + P_IER);
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/* clear interrupt */
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writel(irqtype, devpriv->base_addr + P_ISR);
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writel(irqtype, devpriv->mmio + P_ISR);
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switch (irqtype) {
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case IRQ_RPS1: /* end_of_scan occurs */
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@ -909,7 +909,7 @@ static irqreturn_t s626_irq_handler(int irq, void *d)
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}
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/* enable interrupt */
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writel(irqstatus, devpriv->base_addr + P_IER);
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writel(irqstatus, devpriv->mmio + P_IER);
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spin_unlock_irqrestore(&dev->spinlock, flags);
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return IRQ_HANDLED;
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@ -936,7 +936,7 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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/* Initialize RPS instruction pointer */
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writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
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devpriv->base_addr + P_RPSADDR1);
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devpriv->mmio + P_RPSADDR1);
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/* Construct RPS program in RPSBuf DMA buffer */
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@ -1165,7 +1165,7 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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int n;
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/* interrupt call test */
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/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
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/* writel(IRQ_GPIO3,devpriv->mmio+P_PSR); */
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/* Writing a logical 1 into any of the RPS_PSR bits causes the
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* corresponding interrupt to be generated if enabled
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*/
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@ -1190,26 +1190,26 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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udelay(10);
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/* Start ADC by pulsing GPIO1 low */
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GpioImage = readl(devpriv->base_addr + P_GPIO);
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GpioImage = readl(devpriv->mmio + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* Negate ADC Start command */
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writel(GpioImage | GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
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/* Wait for ADC to complete (GPIO2 is asserted high when */
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/* ADC not busy) and for data from previous conversion to */
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/* shift into FB BUFFER 1 register. */
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/* Wait for ADC done */
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while (!(readl(devpriv->base_addr + P_PSR) & PSR_GPIO2))
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while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data */
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if (n != 0) {
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tmp = readl(devpriv->base_addr + P_FB_BUFFER1);
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tmp = readl(devpriv->mmio + P_FB_BUFFER1);
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data[n - 1] = s626_ai_reg_to_uint(tmp);
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}
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@ -1226,26 +1226,26 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Start a dummy conversion to cause the data from the
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* previous conversion to be shifted in. */
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GpioImage = readl(devpriv->base_addr + P_GPIO);
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GpioImage = readl(devpriv->mmio + P_GPIO);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->mmio + P_GPIO);
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/* Negate ADC Start command */
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writel(GpioImage | GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage | GPIO1_HI, devpriv->mmio + P_GPIO);
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/* Wait for the data to arrive in FB BUFFER 1 register. */
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/* Wait for ADC done */
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while (!(readl(devpriv->base_addr + P_PSR) & PSR_GPIO2))
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while (!(readl(devpriv->mmio + P_PSR) & PSR_GPIO2))
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;
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/* Fetch ADC data from audio interface's input shift register. */
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/* Fetch ADC data */
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if (n != 0) {
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tmp = readl(devpriv->base_addr + P_FB_BUFFER1);
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tmp = readl(devpriv->mmio + P_FB_BUFFER1);
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data[n - 1] = s626_ai_reg_to_uint(tmp);
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}
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@ -1360,10 +1360,10 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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return -EBUSY;
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}
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/* disable interrupt */
|
||||
writel(0, devpriv->base_addr + P_IER);
|
||||
writel(0, devpriv->mmio + P_IER);
|
||||
|
||||
/* clear interrupt request */
|
||||
writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
|
||||
writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->mmio + P_ISR);
|
||||
|
||||
/* clear any pending interrupt */
|
||||
s626_dio_clear_irq(dev);
|
||||
@ -1464,7 +1464,7 @@ static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
|
||||
writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->mmio + P_IER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1585,7 +1585,7 @@ static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
|
||||
s626_mc_disable(dev, MC1_ERPS1, P_MC1);
|
||||
|
||||
/* disable master interrupt */
|
||||
writel(0, devpriv->base_addr + P_IER);
|
||||
writel(0, devpriv->mmio + P_IER);
|
||||
|
||||
devpriv->ai_cmd_running = 0;
|
||||
|
||||
@ -2397,13 +2397,13 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
writel(DEBI_CFG_SLAVE16 |
|
||||
(DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
|
||||
DEBI_SWAP | DEBI_CFG_INTEL,
|
||||
devpriv->base_addr + P_DEBICFG);
|
||||
devpriv->mmio + P_DEBICFG);
|
||||
|
||||
/* Disable MMU paging */
|
||||
writel(DEBI_PAGE_DISABLE, devpriv->base_addr + P_DEBIPAGE);
|
||||
writel(DEBI_PAGE_DISABLE, devpriv->mmio + P_DEBIPAGE);
|
||||
|
||||
/* Init GPIO so that ADC Start* is negated */
|
||||
writel(GPIO_BASE | GPIO1_HI, devpriv->base_addr + P_GPIO);
|
||||
writel(GPIO_BASE | GPIO1_HI, devpriv->mmio + P_GPIO);
|
||||
|
||||
/* I2C device address for onboard eeprom (revb) */
|
||||
devpriv->I2CAdrs = 0xA0;
|
||||
@ -2412,9 +2412,9 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* Issue an I2C ABORT command to halt any I2C
|
||||
* operation in progress and reset BUSY flag.
|
||||
*/
|
||||
writel(I2C_CLKSEL | I2C_ABORT, devpriv->base_addr + P_I2CSTAT);
|
||||
writel(I2C_CLKSEL | I2C_ABORT, devpriv->mmio + P_I2CSTAT);
|
||||
s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
|
||||
while (!(readl(devpriv->base_addr + P_MC2) & MC2_UPLD_IIC))
|
||||
while (!(readl(devpriv->mmio + P_MC2) & MC2_UPLD_IIC))
|
||||
;
|
||||
|
||||
/*
|
||||
@ -2422,7 +2422,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* reg twice to reset all I2C error flags.
|
||||
*/
|
||||
for (i = 0; i < 2; i++) {
|
||||
writel(I2C_CLKSEL, devpriv->base_addr + P_I2CSTAT);
|
||||
writel(I2C_CLKSEL, devpriv->mmio + P_I2CSTAT);
|
||||
s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
|
||||
while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
|
||||
;
|
||||
@ -2434,7 +2434,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* DAC data setup times are satisfied, enable DAC serial
|
||||
* clock out.
|
||||
*/
|
||||
writel(ACON2_INIT, devpriv->base_addr + P_ACON2);
|
||||
writel(ACON2_INIT, devpriv->mmio + P_ACON2);
|
||||
|
||||
/*
|
||||
* Set up TSL1 slot list, which is used to control the
|
||||
@ -2442,11 +2442,11 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* SIB_A1 = store data uint8_t at next available location
|
||||
* in FB BUFFER1 register.
|
||||
*/
|
||||
writel(RSD1 | SIB_A1, devpriv->base_addr + P_TSL1);
|
||||
writel(RSD1 | SIB_A1 | EOS, devpriv->base_addr + P_TSL1 + 4);
|
||||
writel(RSD1 | SIB_A1, devpriv->mmio + P_TSL1);
|
||||
writel(RSD1 | SIB_A1 | EOS, devpriv->mmio + P_TSL1 + 4);
|
||||
|
||||
/* Enable TSL1 slot list so that it executes all the time */
|
||||
writel(ACON1_ADCSTART, devpriv->base_addr + P_ACON1);
|
||||
writel(ACON1_ADCSTART, devpriv->mmio + P_ACON1);
|
||||
|
||||
/*
|
||||
* Initialize RPS registers used for ADC
|
||||
@ -2454,11 +2454,11 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
|
||||
/* Physical start of RPS program */
|
||||
writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
|
||||
devpriv->base_addr + P_RPSADDR1);
|
||||
devpriv->mmio + P_RPSADDR1);
|
||||
/* RPS program performs no explicit mem writes */
|
||||
writel(0, devpriv->base_addr + P_RPSPAGE1);
|
||||
writel(0, devpriv->mmio + P_RPSPAGE1);
|
||||
/* Disable RPS timeouts */
|
||||
writel(0, devpriv->base_addr + P_RPS1_TOUT);
|
||||
writel(0, devpriv->mmio + P_RPS1_TOUT);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
@ -2514,7 +2514,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* burst length = 1 DWORD
|
||||
* threshold = 1 DWORD.
|
||||
*/
|
||||
writel(0, devpriv->base_addr + P_PCI_BT_A);
|
||||
writel(0, devpriv->mmio + P_PCI_BT_A);
|
||||
|
||||
/*
|
||||
* Init Audio2's output DMA physical addresses. The protection
|
||||
@ -2524,9 +2524,9 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
*/
|
||||
pPhysBuf = devpriv->ANABuf.PhysicalBase +
|
||||
(DAC_WDMABUF_OS * sizeof(uint32_t));
|
||||
writel((uint32_t)pPhysBuf, devpriv->base_addr + P_BASEA2_OUT);
|
||||
writel((uint32_t)pPhysBuf, devpriv->mmio + P_BASEA2_OUT);
|
||||
writel((uint32_t)(pPhysBuf + sizeof(uint32_t)),
|
||||
devpriv->base_addr + P_PROTA2_OUT);
|
||||
devpriv->mmio + P_PROTA2_OUT);
|
||||
|
||||
/*
|
||||
* Cache Audio2's output DMA buffer logical address. This is
|
||||
@ -2541,7 +2541,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
* DMAC will automatically halt and its PCI address pointer
|
||||
* will be reset when the protection address is reached.
|
||||
*/
|
||||
writel(8, devpriv->base_addr + P_PAGEA2_OUT);
|
||||
writel(8, devpriv->mmio + P_PAGEA2_OUT);
|
||||
|
||||
/*
|
||||
* Initialize time slot list 2 (TSL2), which is used to control
|
||||
@ -2556,7 +2556,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
*/
|
||||
|
||||
/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
|
||||
writel(XSD2 | RSD3 | SIB_A2 | EOS, devpriv->base_addr + VECTPORT(0));
|
||||
writel(XSD2 | RSD3 | SIB_A2 | EOS, devpriv->mmio + VECTPORT(0));
|
||||
|
||||
/*
|
||||
* Initialize slot 1, which is constant. Slot 1 causes a
|
||||
@ -2568,10 +2568,10 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
*/
|
||||
|
||||
/* Slot 1: Fetch DWORD from Audio2's output FIFO */
|
||||
writel(LF_A2, devpriv->base_addr + VECTPORT(1));
|
||||
writel(LF_A2, devpriv->mmio + VECTPORT(1));
|
||||
|
||||
/* Start DAC's audio interface (TSL2) running */
|
||||
writel(ACON1_DACSTART, devpriv->base_addr + P_ACON1);
|
||||
writel(ACON1_DACSTART, devpriv->mmio + P_ACON1);
|
||||
|
||||
/*
|
||||
* Init Trim DACs to calibrated values. Do it twice because the
|
||||
@ -2612,7 +2612,7 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
s626_dio_init(dev);
|
||||
|
||||
/* enable interrupt test */
|
||||
/* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); */
|
||||
/* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->mmio + P_IER); */
|
||||
}
|
||||
|
||||
static int s626_auto_attach(struct comedi_device *dev,
|
||||
@ -2634,16 +2634,16 @@ static int s626_auto_attach(struct comedi_device *dev,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
devpriv->base_addr = ioremap(pci_resource_start(pcidev, 0),
|
||||
pci_resource_len(pcidev, 0));
|
||||
if (!devpriv->base_addr)
|
||||
devpriv->mmio = ioremap(pci_resource_start(pcidev, 0),
|
||||
pci_resource_len(pcidev, 0));
|
||||
if (!devpriv->mmio)
|
||||
return -ENOMEM;
|
||||
|
||||
/* disable master interrupt */
|
||||
writel(0, devpriv->base_addr + P_IER);
|
||||
writel(0, devpriv->mmio + P_IER);
|
||||
|
||||
/* soft reset */
|
||||
writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
|
||||
writel(MC1_SOFT_RESET, devpriv->mmio + P_MC1);
|
||||
|
||||
/* DMA FIXME DMA// */
|
||||
|
||||
@ -2752,20 +2752,20 @@ static void s626_detach(struct comedi_device *dev)
|
||||
/* stop ai_command */
|
||||
devpriv->ai_cmd_running = 0;
|
||||
|
||||
if (devpriv->base_addr) {
|
||||
if (devpriv->mmio) {
|
||||
/* interrupt mask */
|
||||
/* Disable master interrupt */
|
||||
writel(0, devpriv->base_addr + P_IER);
|
||||
writel(0, devpriv->mmio + P_IER);
|
||||
/* Clear board's IRQ status flag */
|
||||
writel(IRQ_GPIO3 | IRQ_RPS1,
|
||||
devpriv->base_addr + P_ISR);
|
||||
devpriv->mmio + P_ISR);
|
||||
|
||||
/* Disable the watchdog timer and battery charger. */
|
||||
WriteMISC2(dev, 0);
|
||||
|
||||
/* Close all interfaces on 7146 device */
|
||||
writel(MC1_SHUTDOWN, devpriv->base_addr + P_MC1);
|
||||
writel(ACON1_BASE, devpriv->base_addr + P_ACON1);
|
||||
writel(MC1_SHUTDOWN, devpriv->mmio + P_MC1);
|
||||
writel(ACON1_BASE, devpriv->mmio + P_ACON1);
|
||||
|
||||
CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
|
||||
CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
|
||||
@ -2773,8 +2773,8 @@ static void s626_detach(struct comedi_device *dev)
|
||||
|
||||
if (dev->irq)
|
||||
free_irq(dev->irq, dev);
|
||||
if (devpriv->base_addr)
|
||||
iounmap(devpriv->base_addr);
|
||||
if (devpriv->mmio)
|
||||
iounmap(devpriv->mmio);
|
||||
}
|
||||
comedi_pci_disable(dev);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user