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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ASoC: rt5677: Allow arbitrary block read/write via SPI
Added rt5677_spi_read() and refactored rt5677_spi_write() so that an arbitrary block in the DSP address space can be read/written via SPI. For example, this allows us to load an ELF DSP firmware with sparse sections, and stream audio samples from DSP ring buffer. Signed-off-by: Ben Zhang <benzh@chromium.org> Acked-by: Oder Chiou <oder_chiou@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ben Zhang
Mark Brown
parent
f8163c8673
commit
7d4d443eb4
@ -31,84 +31,197 @@
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#include "rt5677-spi.h"
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static struct spi_device *g_spi;
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#define RT5677_SPI_BURST_LEN 240
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#define RT5677_SPI_HEADER 5
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#define RT5677_SPI_FREQ 6000000
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/**
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* rt5677_spi_write - Write data to SPI.
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* @txbuf: Data Buffer for writing.
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* @len: Data length.
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*
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*
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* Returns true for success.
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/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
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* DataPhase word size of 16-bit commands is 2 bytes.
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* DataPhase word size of 32-bit commands is 4 bytes.
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* DataPhase word size of burst commands is 8 bytes.
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* The DSP CPU is little-endian.
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*/
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int rt5677_spi_write(u8 *txbuf, size_t len)
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#define RT5677_SPI_WRITE_BURST 0x5
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#define RT5677_SPI_READ_BURST 0x4
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#define RT5677_SPI_WRITE_32 0x3
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#define RT5677_SPI_READ_32 0x2
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#define RT5677_SPI_WRITE_16 0x1
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#define RT5677_SPI_READ_16 0x0
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static struct spi_device *g_spi;
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static DEFINE_MUTEX(spi_mutex);
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/* Select a suitable transfer command for the next transfer to ensure
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* the transfer address is always naturally aligned while minimizing
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* the total number of transfers required.
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*
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* 3 transfer commands are available:
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* RT5677_SPI_READ/WRITE_16: Transfer 2 bytes
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* RT5677_SPI_READ/WRITE_32: Transfer 4 bytes
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* RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
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*
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* For example, reading 260 bytes at 0x60030002 uses the following commands:
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* 0x60030002 RT5677_SPI_READ_16 2 bytes
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* 0x60030004 RT5677_SPI_READ_32 4 bytes
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* 0x60030008 RT5677_SPI_READ_BURST 240 bytes
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* 0x600300F8 RT5677_SPI_READ_BURST 8 bytes
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* 0x60030100 RT5677_SPI_READ_32 4 bytes
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* 0x60030104 RT5677_SPI_READ_16 2 bytes
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*
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* Input:
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* @read: true for read commands; false for write commands
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* @align: alignment of the next transfer address
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* @remain: number of bytes remaining to transfer
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*
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* Output:
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* @len: number of bytes to transfer with the selected command
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* Returns the selected command
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*/
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static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
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{
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int status;
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u8 cmd;
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status = spi_write(g_spi, txbuf, len);
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if (align == 2 || align == 6 || remain == 2) {
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cmd = RT5677_SPI_READ_16;
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*len = 2;
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} else if (align == 4 || remain <= 6) {
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cmd = RT5677_SPI_READ_32;
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*len = 4;
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} else {
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cmd = RT5677_SPI_READ_BURST;
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*len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN);
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}
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return read ? cmd : cmd + 1;
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}
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if (status)
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dev_err(&g_spi->dev, "rt5677_spi_write error %d\n", status);
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/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
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* If srclen < dstlen, zeros are padded.
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*/
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static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
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{
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u32 w, i, si;
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u32 word_size = min_t(u32, dstlen, 8);
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for (w = 0; w < dstlen; w += word_size) {
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for (i = 0; i < word_size; i++) {
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si = w + word_size - i - 1;
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dst[w + i] = si < srclen ? src[si] : 0;
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}
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}
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}
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/* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */
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int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
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{
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u32 offset;
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int status = 0;
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struct spi_transfer t[2];
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struct spi_message m;
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/* +4 bytes is for the DummyPhase following the AddressPhase */
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u8 header[RT5677_SPI_HEADER + 4];
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u8 body[RT5677_SPI_BURST_LEN];
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u8 spi_cmd;
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u8 *cb = rxbuf;
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if (!g_spi)
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return -ENODEV;
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if ((addr & 1) || (len & 1)) {
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dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
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return -EACCES;
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}
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memset(t, 0, sizeof(t));
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t[0].tx_buf = header;
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t[0].len = sizeof(header);
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t[0].speed_hz = RT5677_SPI_FREQ;
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t[1].rx_buf = body;
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t[1].speed_hz = RT5677_SPI_FREQ;
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spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
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for (offset = 0; offset < len; offset += t[1].len) {
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spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
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len - offset, &t[1].len);
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/* Construct SPI message header */
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header[0] = spi_cmd;
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header[1] = ((addr + offset) & 0xff000000) >> 24;
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header[2] = ((addr + offset) & 0x00ff0000) >> 16;
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header[3] = ((addr + offset) & 0x0000ff00) >> 8;
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header[4] = ((addr + offset) & 0x000000ff) >> 0;
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mutex_lock(&spi_mutex);
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status |= spi_sync(g_spi, &m);
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mutex_unlock(&spi_mutex);
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/* Copy data back to caller buffer */
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rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len);
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}
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return status;
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}
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EXPORT_SYMBOL_GPL(rt5677_spi_read);
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/* Write DSP address space using SPI. addr has to be 2-byte aligned.
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* If len is not 2-byte aligned, an extra byte of zero is written at the end
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* as padding.
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*/
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int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
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{
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u32 offset, len_with_pad = len;
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int status = 0;
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struct spi_transfer t;
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struct spi_message m;
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/* +1 byte is for the DummyPhase following the DataPhase */
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u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
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u8 *body = buf + RT5677_SPI_HEADER;
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u8 spi_cmd;
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const u8 *cb = txbuf;
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if (!g_spi)
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return -ENODEV;
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if (addr & 1) {
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dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
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return -EACCES;
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}
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if (len & 1)
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len_with_pad = len + 1;
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memset(&t, 0, sizeof(t));
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t.tx_buf = buf;
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t.speed_hz = RT5677_SPI_FREQ;
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spi_message_init_with_transfers(&m, &t, 1);
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for (offset = 0; offset < len_with_pad;) {
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spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
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len_with_pad - offset, &t.len);
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/* Construct SPI message header */
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buf[0] = spi_cmd;
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buf[1] = ((addr + offset) & 0xff000000) >> 24;
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buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
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buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
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buf[4] = ((addr + offset) & 0x000000ff) >> 0;
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/* Fetch data from caller buffer */
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rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
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offset += t.len;
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t.len += RT5677_SPI_HEADER + 1;
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mutex_lock(&spi_mutex);
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status |= spi_sync(g_spi, &m);
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mutex_unlock(&spi_mutex);
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}
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return status;
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}
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EXPORT_SYMBOL_GPL(rt5677_spi_write);
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/**
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* rt5677_spi_burst_write - Write data to SPI by rt5677 dsp memory address.
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* @addr: Start address.
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* @txbuf: Data Buffer for writng.
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* @len: Data length, it must be a multiple of 8.
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*
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*
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* Returns true for success.
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*/
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int rt5677_spi_burst_write(u32 addr, const struct firmware *fw)
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int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
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{
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u8 spi_cmd = RT5677_SPI_CMD_BURST_WRITE;
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u8 *write_buf;
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unsigned int i, end, offset = 0;
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write_buf = kmalloc(RT5677_SPI_BUF_LEN + 6, GFP_KERNEL);
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if (write_buf == NULL)
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return -ENOMEM;
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while (offset < fw->size) {
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if (offset + RT5677_SPI_BUF_LEN <= fw->size)
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end = RT5677_SPI_BUF_LEN;
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else
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end = fw->size % RT5677_SPI_BUF_LEN;
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write_buf[0] = spi_cmd;
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write_buf[1] = ((addr + offset) & 0xff000000) >> 24;
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write_buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
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write_buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
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write_buf[4] = ((addr + offset) & 0x000000ff) >> 0;
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for (i = 0; i < end; i += 8) {
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write_buf[i + 12] = fw->data[offset + i + 0];
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write_buf[i + 11] = fw->data[offset + i + 1];
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write_buf[i + 10] = fw->data[offset + i + 2];
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write_buf[i + 9] = fw->data[offset + i + 3];
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write_buf[i + 8] = fw->data[offset + i + 4];
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write_buf[i + 7] = fw->data[offset + i + 5];
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write_buf[i + 6] = fw->data[offset + i + 6];
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write_buf[i + 5] = fw->data[offset + i + 7];
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}
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write_buf[end + 5] = spi_cmd;
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rt5677_spi_write(write_buf, end + 6);
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offset += RT5677_SPI_BUF_LEN;
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}
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kfree(write_buf);
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return 0;
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return rt5677_spi_write(addr, fw->data, fw->size);
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}
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EXPORT_SYMBOL_GPL(rt5677_spi_burst_write);
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EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
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static int rt5677_spi_probe(struct spi_device *spi)
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{
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@ -12,10 +12,8 @@
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#ifndef __RT5677_SPI_H__
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#define __RT5677_SPI_H__
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#define RT5677_SPI_BUF_LEN 240
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#define RT5677_SPI_CMD_BURST_WRITE 0x05
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int rt5677_spi_write(u8 *txbuf, size_t len);
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int rt5677_spi_burst_write(u32 addr, const struct firmware *fw);
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int rt5677_spi_read(u32 addr, void *rxbuf, size_t len);
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int rt5677_spi_write(u32 addr, const void *txbuf, size_t len);
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int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw);
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#endif /* __RT5677_SPI_H__ */
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@ -745,14 +745,14 @@ static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
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ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
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codec->dev);
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if (ret == 0) {
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rt5677_spi_burst_write(0x50000000, rt5677->fw1);
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rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
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release_firmware(rt5677->fw1);
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}
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ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
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codec->dev);
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if (ret == 0) {
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rt5677_spi_burst_write(0x60000000, rt5677->fw2);
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rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
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release_firmware(rt5677->fw2);
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}
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