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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
Fix data read/write error in HS200 mode due to chip DLL lock phase shift Signed-off-by: Shirley Her <shirley.her@bayhubtech.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Shirley Her (SC)
Ulf Hansson
parent
908fd50813
commit
7d44061704
@ -11,6 +11,7 @@
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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@ -55,9 +56,18 @@
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#define O2_PLL_FORCE_ACTIVE BIT(18)
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#define O2_PLL_LOCK_STATUS BIT(14)
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#define O2_PLL_SOFT_RESET BIT(12)
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#define O2_DLL_LOCK_STATUS BIT(11)
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#define O2_SD_DETECT_SETTING 0x324
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static const u32 dmdn_table[] = {0x2B1C0000,
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0x2C1A0000, 0x371B0000, 0x35100000};
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#define DMDN_SZ ARRAY_SIZE(dmdn_table)
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struct o2_host {
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u8 dll_adjust_count;
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};
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static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
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{
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ktime_t timeout;
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@ -133,7 +143,8 @@ static int sdhci_o2_get_cd(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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sdhci_o2_enable_internal_clock(host);
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if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
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sdhci_o2_enable_internal_clock(host);
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return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
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}
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@ -152,6 +163,25 @@ static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
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O2_SD_PLL_SETTING, scratch_32);
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}
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static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
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{
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return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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}
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/*
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* This function is used to detect dll lock status.
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* Since the dll lock status bit will toggle randomly
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* with very short interval which needs to be polled
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* as fast as possible. Set sleep_us as 1 microsecond.
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*/
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static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
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{
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u32 scratch32 = 0;
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return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
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scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
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}
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static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
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{
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u16 reg;
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@ -189,6 +219,83 @@ static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
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sdhci_reset_tuning(host);
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}
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/*
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* This function is used to fix o2 dll shift issue.
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* It isn't necessary to detect card present before recovery.
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* Firstly, it is used by bht emmc card, which is embedded.
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* Second, before call recovery card present will be detected
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* outside of the execute tuning function.
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*/
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static int sdhci_o2_dll_recovery(struct sdhci_host *host)
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{
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int ret = 0;
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u8 scratch_8 = 0;
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u32 scratch_32 = 0;
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct sdhci_pci_chip *chip = slot->chip;
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struct o2_host *o2_host = sdhci_pci_priv(slot);
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/* UnLock WP */
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pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch_8);
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scratch_8 &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
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/* Disable clock */
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sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
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/* PLL software reset */
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scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
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scratch_32 |= O2_PLL_SOFT_RESET;
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sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
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pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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/* Enable Base Clk setting change */
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scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
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pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
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o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
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/* Enable internal clock */
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scratch_8 = SDHCI_CLOCK_INT_EN;
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sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
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if (sdhci_o2_get_cd(host->mmc)) {
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/*
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* need wait at least 5ms for dll status stable,
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* after enable internal clock
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*/
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usleep_range(5000, 6000);
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if (sdhci_o2_wait_dll_detect_lock(host)) {
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scratch_8 |= SDHCI_CLOCK_CARD_EN;
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sdhci_writeb(host, scratch_8,
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SDHCI_CLOCK_CONTROL);
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ret = 1;
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} else {
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pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
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mmc_hostname(host->mmc),
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o2_host->dll_adjust_count);
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}
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} else {
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pr_err("%s: card present detect failed.\n",
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mmc_hostname(host->mmc));
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break;
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}
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o2_host->dll_adjust_count++;
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}
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if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
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pr_err("%s: DLL adjust over max times\n",
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mmc_hostname(host->mmc));
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/* Lock WP */
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pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch_8);
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scratch_8 |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
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return ret;
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}
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static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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@ -203,7 +310,16 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
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if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
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return -EINVAL;
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/*
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* Judge the tuning reason, whether caused by dll shift
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* If cause by dll shift, should call sdhci_o2_dll_recovery
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*/
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if (!sdhci_o2_wait_dll_detect_lock(host))
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if (!sdhci_o2_dll_recovery(host)) {
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pr_err("%s: o2 dll recovery failed\n",
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mmc_hostname(host->mmc));
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return -EINVAL;
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}
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/*
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* o2 sdhci host didn't support 8bit emmc tuning
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*/
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@ -371,6 +487,7 @@ static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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sdhci_o2_enable_internal_clock(host);
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if (sdhci_o2_get_cd(host->mmc)) {
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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@ -396,12 +513,14 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
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{
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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struct o2_host *o2_host = sdhci_pci_priv(slot);
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u32 reg, caps;
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int ret;
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chip = slot->chip;
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host = slot->host;
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o2_host->dll_adjust_count = 0;
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caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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/*
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@ -688,4 +807,5 @@ const struct sdhci_pci_fixes sdhci_o2 = {
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.resume = sdhci_pci_o2_resume,
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#endif
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.ops = &sdhci_pci_o2_ops,
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.priv_size = sizeof(struct o2_host),
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};
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