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mlxsw: reg: Add Router Algorithmic LPM Unicast Host Table Dump register
The RAUHTD register allows dumping entries from the Router Unicast Host Table. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yotam Gigi
David S. Miller
parent
4457b3df3f
commit
7cf2c205d7
@ -4023,6 +4023,151 @@ static inline void mlxsw_reg_rauht_pack4(char *payload,
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mlxsw_reg_rauht_dip4_set(payload, dip);
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}
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/* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
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* ----------------------------------------------------------------
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* The RAUHTD register allows dumping entries from the Router Unicast Host
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* Table. For a given session an entry is dumped no more than one time. The
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* first RAUHTD access after reset is a new session. A session ends when the
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* num_rec response is smaller than num_rec request or for IPv4 when the
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* num_entries is smaller than 4. The clear activity affect the current session
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* or the last session if a new session has not started.
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*/
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#define MLXSW_REG_RAUHTD_ID 0x8018
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#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
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#define MLXSW_REG_RAUHTD_REC_LEN 0x20
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#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
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#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
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MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
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#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
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static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
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.id = MLXSW_REG_RAUHTD_ID,
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.len = MLXSW_REG_RAUHTD_LEN,
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};
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#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
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#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
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/* reg_rauhtd_filter_fields
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* if a bit is '0' then the relevant field is ignored and dump is done
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* regardless of the field value
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* Bit0 - filter by activity: entry_a
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* Bit3 - filter by entry rip: entry_rif
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
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enum mlxsw_reg_rauhtd_op {
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MLXSW_REG_RAUHTD_OP_DUMP,
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MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
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};
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/* reg_rauhtd_op
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* Access: OP
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*/
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MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
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/* reg_rauhtd_num_rec
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* At request: number of records requested
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* At response: number of records dumped
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* For IPv4, each record has 4 entries at request and up to 4 entries
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* at response
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* Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
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/* reg_rauhtd_entry_a
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* Dump only if activity has value of entry_a
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* Reserved if filter_fields bit0 is '0'
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
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enum mlxsw_reg_rauhtd_type {
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MLXSW_REG_RAUHTD_TYPE_IPV4,
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MLXSW_REG_RAUHTD_TYPE_IPV6,
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};
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/* reg_rauhtd_type
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* Dump only if record type is:
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* 0 - IPv4
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* 1 - IPv6
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
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/* reg_rauhtd_entry_rif
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* Dump only if RIF has value of entry_rif
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* Reserved if filter_fields bit3 is '0'
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
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static inline void mlxsw_reg_rauhtd_pack(char *payload,
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enum mlxsw_reg_rauhtd_type type)
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{
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MLXSW_REG_ZERO(rauhtd, payload);
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mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
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mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
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mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
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mlxsw_reg_rauhtd_entry_a_set(payload, 1);
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mlxsw_reg_rauhtd_type_set(payload, type);
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}
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/* reg_rauhtd_ipv4_rec_num_entries
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* Number of valid entries in this record:
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* 0 - 1 valid entry
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* 1 - 2 valid entries
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* 2 - 3 valid entries
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* 3 - 4 valid entries
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* Access: RO
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*/
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MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
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MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
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MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
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/* reg_rauhtd_rec_type
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* Record type.
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* 0 - IPv4
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* 1 - IPv6
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* Access: RO
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*/
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MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
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MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
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#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
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/* reg_rauhtd_ipv4_ent_a
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* Activity. Set for new entries. Set if a packet lookup has hit on the
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* specific entry.
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* Access: RO
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*/
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MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
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MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
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/* reg_rauhtd_ipv4_ent_rif
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* Router interface.
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* Access: RO
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*/
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MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
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16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
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/* reg_rauhtd_ipv4_ent_dip
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* Destination IPv4 address.
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* Access: RO
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*/
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MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
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32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
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static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
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int ent_index, u16 *p_rif,
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u32 *p_dip)
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{
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*p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
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*p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
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}
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/* MFCR - Management Fan Control Register
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* --------------------------------------
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* This register controls the settings of the Fan Speed PWM mechanism.
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@ -4775,6 +4920,8 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "RALUE";
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case MLXSW_REG_RAUHT_ID:
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return "RAUHT";
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case MLXSW_REG_RAUHTD_ID:
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return "RAUHTD";
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case MLXSW_REG_MFCR_ID:
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return "MFCR";
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case MLXSW_REG_MFSC_ID:
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