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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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carl9170: fix timekeeping for HW_COUNTER firmwares
AR9170_PWR_REG_PLL_ADDAC is used to set the main clock divisor which affects the AHB/CPU speed. Because this would interfere with the firmware internal timekeeping, the function has to be moved into the firmware. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -282,6 +282,7 @@ struct ar9170 {
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bool rx_stream;
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bool tx_stream;
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bool rx_filter;
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bool hw_counters;
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unsigned int mem_blocks;
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unsigned int mem_block_size;
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unsigned int rx_size;
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@ -266,6 +266,9 @@ static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len)
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FIF_PROMISC_IN_BSS;
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}
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if (SUPP(CARL9170FW_HW_COUNTERS))
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ar->fw.hw_counters = true;
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if (SUPP(CARL9170FW_WOL))
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device_set_wakeup_enable(&ar->udev->dev, true);
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@ -578,11 +578,10 @@ static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
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if (err)
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return err;
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/* XXX: remove magic! */
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if (is_2ghz)
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err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163);
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else
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err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143);
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if (!ar->fw.hw_counters) {
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err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC,
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is_2ghz ? 0x5163 : 0x5143);
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}
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return err;
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}
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