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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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x86/pci/mrst: Cleanup checkpatch.pl warnings
This patch fixes warning and errors found by checkpatch.pl: * replace asm/acpi.h, asm/io.h and asm/smp.h with linux/acpi.h, linux/io.h and linux/smp.h respectively * remove explicit initialization to 0 of a static global variable * replace printk(KERN_INFO ...) with pr_info * use tabs instead of spaces for indentation * arrange comments so that they adhere to Documentation/CodingStyle [bhelgaas: capitalize "PCI", "Langwell", "Lincroft" consistently] Signed-off-by: Valentina Manea <valentina.manea.m@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ingo Molnar <mingo@kernel.org>
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@ -23,11 +23,11 @@
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <asm/acpi.h>
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#include <asm/segment.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/pci_x86.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
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@ -43,7 +43,7 @@
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#define PCI_FIXED_BAR_4_SIZE 0x14
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#define PCI_FIXED_BAR_5_SIZE 0x1c
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static int pci_soc_mode = 0;
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static int pci_soc_mode;
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/**
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* fixed_bar_cap - return the offset of the fixed BAR cap if found
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@ -141,7 +141,8 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
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*/
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static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
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{
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/* This is a workaround for A0 LNC bug where PCI status register does
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/*
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* This is a workaround for A0 LNC bug where PCI status register does
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* not have new CAP bit set. can not be written by SW either.
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*
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* PCI header type in real LNC indicates a single function device, this
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@ -154,7 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
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|| devfn == PCI_DEVFN(0, 0)
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|| devfn == PCI_DEVFN(3, 0)))
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return 1;
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return 0; /* langwell on others */
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return 0; /* Langwell on others */
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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@ -172,7 +173,8 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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{
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int offset;
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/* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
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/*
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* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
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* to ROM BAR return 0 then being ignored.
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*/
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if (where == PCI_ROM_ADDRESS)
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@ -210,7 +212,8 @@ static int mrst_pci_irq_enable(struct pci_dev *dev)
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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/* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
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/*
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* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
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* IOAPIC RTE entries, so we just enable RTE for the device.
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*/
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irq_attr.ioapic = mp_find_ioapic(dev->irq);
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@ -235,7 +238,7 @@ struct pci_ops pci_mrst_ops = {
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*/
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int __init pci_mrst_init(void)
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{
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printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");
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pr_info("Intel MID platform detected, using MID PCI ops\n");
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pci_mmcfg_late_init();
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pcibios_enable_irq = mrst_pci_irq_enable;
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pci_root_ops = pci_mrst_ops;
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@ -244,17 +247,21 @@ int __init pci_mrst_init(void)
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return 1;
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}
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/* Langwell devices are not true pci devices, they are not subject to 10 ms
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* d3 to d0 delay required by pci spec.
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/*
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* Langwell devices are not true PCI devices; they are not subject to 10 ms
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* d3 to d0 delay required by PCI spec.
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*/
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static void pci_d3delay_fixup(struct pci_dev *dev)
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{
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/* PCI fixups are effectively decided compile time. If we have a dual
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SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */
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if (!pci_soc_mode)
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return;
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/* true pci devices in lincroft should allow type 1 access, the rest
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* are langwell fake pci devices.
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/*
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* PCI fixups are effectively decided compile time. If we have a dual
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* SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
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*/
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if (!pci_soc_mode)
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return;
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/*
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* True PCI devices in Lincroft should allow type 1 access, the rest
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* are Langwell fake PCI devices.
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*/
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if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
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return;
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