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powerpc/mpic: allow coreint to be determined by MPIC version
This will be used by the qemu-e500 platform, as the MPIC version (and thus whether we have coreint) depends on how QEMU is configured. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -1182,6 +1182,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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const char *vers;
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const u32 *psrc;
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u32 last_irq;
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u32 fsl_version = 0;
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/* Default MPIC search parameters */
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static const struct of_device_id __initconst mpic_device_id[] = {
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@ -1314,7 +1315,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
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if (mpic->flags & MPIC_FSL) {
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u32 brr1, version;
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u32 brr1;
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int ret;
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/*
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@ -1327,7 +1328,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
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MPIC_FSL_BRR1);
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version = brr1 & MPIC_FSL_BRR1_VER;
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fsl_version = brr1 & MPIC_FSL_BRR1_VER;
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/* Error interrupt mask register (EIMR) is required for
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* handling individual device error interrupts. EIMR
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@ -1342,11 +1343,30 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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* is the number of vectors which have been consumed by
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* ipis and timer interrupts.
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*/
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if (version >= 0x401) {
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if (fsl_version >= 0x401) {
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ret = mpic_setup_error_int(mpic, intvec_top - 12);
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if (ret)
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return NULL;
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}
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}
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/*
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* EPR is only available starting with v4.0. To support
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* platforms that don't know the MPIC version at compile-time,
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* such as qemu-e500, turn off coreint if this MPIC doesn't
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* support it. Note that we never enable it if it wasn't
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* requested in the first place.
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*
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* This is done outside the MPIC_FSL check, so that we
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* also disable coreint if the MPIC node doesn't have
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* an "fsl,mpic" compatible at all. This will be the case
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* with device trees generated by older versions of QEMU.
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* fsl_version will be zero if MPIC_FSL is not set.
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*/
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if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
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WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
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ppc_md.get_irq = mpic_get_irq;
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}
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/* Reset */
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