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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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RDMA/hns: Fill sq wqe context of ud type in hip08
This patch mainly configure the fields of sq wqe of ud type when posting wr of gsi qp type. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
oulijun
Jason Gunthorpe
parent
0fa95a9a71
commit
7bdee4158b
@ -51,26 +51,99 @@ static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
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dseg->len = cpu_to_le32(sg->length);
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dseg->len = cpu_to_le32(sg->length);
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}
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}
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static int set_rwqe_data_seg(struct ib_qp *ibqp, struct ib_send_wr *wr,
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struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
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void *wqe, unsigned int *sge_ind,
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struct ib_send_wr **bad_wr)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
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struct hns_roce_v2_wqe_data_seg *dseg = wqe;
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struct hns_roce_qp *qp = to_hr_qp(ibqp);
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int i;
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if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
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if (rc_sq_wqe->msg_len > hr_dev->caps.max_sq_inline) {
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*bad_wr = wr;
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dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
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rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
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return -EINVAL;
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}
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for (i = 0; i < wr->num_sge; i++) {
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memcpy(wqe, ((void *)wr->sg_list[i].addr),
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wr->sg_list[i].length);
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wqe += wr->sg_list[i].length;
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}
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roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
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1);
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} else {
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if (wr->num_sge <= 2) {
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for (i = 0; i < wr->num_sge; i++) {
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if (likely(wr->sg_list[i].length)) {
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set_data_seg_v2(dseg, wr->sg_list + i);
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dseg++;
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}
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}
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} else {
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roce_set_field(rc_sq_wqe->byte_20,
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V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
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V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
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(*sge_ind) & (qp->sge.sge_cnt - 1));
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for (i = 0; i < 2; i++) {
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if (likely(wr->sg_list[i].length)) {
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set_data_seg_v2(dseg, wr->sg_list + i);
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dseg++;
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}
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}
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dseg = get_send_extend_sge(qp,
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(*sge_ind) & (qp->sge.sge_cnt - 1));
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for (i = 0; i < wr->num_sge - 2; i++) {
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if (likely(wr->sg_list[i + 2].length)) {
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set_data_seg_v2(dseg,
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wr->sg_list + 2 + i);
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dseg++;
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(*sge_ind)++;
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}
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}
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}
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roce_set_field(rc_sq_wqe->byte_16,
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V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
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V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
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}
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return 0;
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}
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static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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struct ib_send_wr **bad_wr)
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struct ib_send_wr **bad_wr)
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{
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
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struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
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struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
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struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
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struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
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struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
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struct hns_roce_qp *qp = to_hr_qp(ibqp);
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struct hns_roce_qp *qp = to_hr_qp(ibqp);
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struct hns_roce_v2_wqe_data_seg *dseg;
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struct hns_roce_v2_wqe_data_seg *dseg;
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struct device *dev = hr_dev->dev;
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struct device *dev = hr_dev->dev;
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struct hns_roce_v2_db sq_db;
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struct hns_roce_v2_db sq_db;
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unsigned int sge_ind = 0;
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unsigned int sge_ind = 0;
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unsigned int wqe_sz = 0;
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unsigned int owner_bit;
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unsigned int owner_bit;
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unsigned long flags;
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unsigned long flags;
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unsigned int ind;
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unsigned int ind;
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void *wqe = NULL;
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void *wqe = NULL;
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bool loopback;
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int ret = 0;
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int ret = 0;
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u8 *smac;
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int nreq;
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int nreq;
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int i;
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int i;
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if (unlikely(ibqp->qp_type != IB_QPT_RC)) {
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if (unlikely(ibqp->qp_type != IB_QPT_RC &&
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ibqp->qp_type != IB_QPT_GSI &&
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ibqp->qp_type != IB_QPT_UD)) {
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dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
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dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
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*bad_wr = NULL;
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*bad_wr = NULL;
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return -EOPNOTSUPP;
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return -EOPNOTSUPP;
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@ -107,6 +180,133 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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wr->wr_id;
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wr->wr_id;
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owner_bit = ~(qp->sq.head >> ilog2(qp->sq.wqe_cnt)) & 0x1;
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owner_bit = ~(qp->sq.head >> ilog2(qp->sq.wqe_cnt)) & 0x1;
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/* Corresponding to the QP type, wqe process separately */
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if (ibqp->qp_type == IB_QPT_GSI) {
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ud_sq_wqe = wqe;
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memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
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roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
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V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
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roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
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V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
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roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
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V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
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roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
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V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
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roce_set_field(ud_sq_wqe->byte_48,
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V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
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V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
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ah->av.mac[4]);
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roce_set_field(ud_sq_wqe->byte_48,
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V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
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V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
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ah->av.mac[5]);
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/* MAC loopback */
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smac = (u8 *)hr_dev->dev_addr[qp->port];
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loopback = ether_addr_equal_unaligned(ah->av.mac,
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smac) ? 1 : 0;
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roce_set_bit(ud_sq_wqe->byte_40,
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V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
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roce_set_field(ud_sq_wqe->byte_4,
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V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
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V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
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HNS_ROCE_V2_WQE_OP_SEND);
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for (i = 0; i < wr->num_sge; i++)
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ud_sq_wqe->msg_len += wr->sg_list[i].length;
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ud_sq_wqe->immtdata = send_ieth(wr);
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/* Set sig attr */
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roce_set_bit(ud_sq_wqe->byte_4,
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V2_UD_SEND_WQE_BYTE_4_CQE_S,
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(wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
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/* Set se attr */
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roce_set_bit(ud_sq_wqe->byte_4,
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V2_UD_SEND_WQE_BYTE_4_SE_S,
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(wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
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roce_set_bit(ud_sq_wqe->byte_4,
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V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
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roce_set_field(ud_sq_wqe->byte_16,
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V2_UD_SEND_WQE_BYTE_16_PD_M,
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V2_UD_SEND_WQE_BYTE_16_PD_S,
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to_hr_pd(ibqp->pd)->pdn);
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roce_set_field(ud_sq_wqe->byte_16,
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V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
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V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
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wr->num_sge);
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roce_set_field(ud_sq_wqe->byte_20,
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V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
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V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
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sge_ind & (qp->sge.sge_cnt - 1));
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roce_set_field(ud_sq_wqe->byte_24,
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V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
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V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
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ud_sq_wqe->qkey =
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cpu_to_be32(ud_wr(wr)->remote_qkey & 0x80000000) ?
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qp->qkey : ud_wr(wr)->remote_qkey;
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roce_set_field(ud_sq_wqe->byte_32,
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V2_UD_SEND_WQE_BYTE_32_DQPN_M,
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V2_UD_SEND_WQE_BYTE_32_DQPN_S,
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ud_wr(wr)->remote_qpn);
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roce_set_field(ud_sq_wqe->byte_36,
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V2_UD_SEND_WQE_BYTE_36_VLAN_M,
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V2_UD_SEND_WQE_BYTE_36_VLAN_S,
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ah->av.vlan);
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roce_set_field(ud_sq_wqe->byte_36,
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V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
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V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
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ah->av.hop_limit);
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roce_set_field(ud_sq_wqe->byte_36,
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V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
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V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
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0);
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roce_set_field(ud_sq_wqe->byte_36,
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V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
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V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
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0);
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roce_set_field(ud_sq_wqe->byte_40,
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V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
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V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, 0);
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roce_set_field(ud_sq_wqe->byte_40,
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V2_UD_SEND_WQE_BYTE_40_SL_M,
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V2_UD_SEND_WQE_BYTE_40_SL_S,
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ah->av.sl_tclass_flowlabel >>
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HNS_ROCE_SL_SHIFT);
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roce_set_field(ud_sq_wqe->byte_40,
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V2_UD_SEND_WQE_BYTE_40_PORTN_M,
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V2_UD_SEND_WQE_BYTE_40_PORTN_S,
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qp->port);
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roce_set_field(ud_sq_wqe->byte_48,
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V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
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V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
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hns_get_gid_index(hr_dev, qp->phy_port,
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ah->av.gid_index));
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memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
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GID_LEN_V2);
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dseg = get_send_extend_sge(qp,
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sge_ind & (qp->sge.sge_cnt - 1));
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for (i = 0; i < wr->num_sge; i++) {
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set_data_seg_v2(dseg + i, wr->sg_list + i);
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sge_ind++;
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}
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ind++;
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} else if (ibqp->qp_type == IB_QPT_RC) {
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rc_sq_wqe = wqe;
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rc_sq_wqe = wqe;
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memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
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memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
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for (i = 0; i < wr->num_sge; i++)
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for (i = 0; i < wr->num_sge; i++)
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@ -114,17 +314,20 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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rc_sq_wqe->inv_key_immtdata = send_ieth(wr);
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rc_sq_wqe->inv_key_immtdata = send_ieth(wr);
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roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_SEND_WQE_BYTE_4_FENCE_S,
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(wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
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(wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_SEND_WQE_BYTE_4_SE_S,
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(wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
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(wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_SEND_WQE_BYTE_4_CQE_S,
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(wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
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(wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
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roce_set_bit(rc_sq_wqe->byte_4,
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owner_bit);
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V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
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switch (wr->opcode) {
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switch (wr->opcode) {
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case IB_WR_RDMA_READ:
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case IB_WR_RDMA_READ:
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@ -132,24 +335,30 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
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V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
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V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
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V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
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HNS_ROCE_V2_WQE_OP_RDMA_READ);
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HNS_ROCE_V2_WQE_OP_RDMA_READ);
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rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
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rc_sq_wqe->rkey =
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rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
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cpu_to_le32(rdma_wr(wr)->rkey);
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||||||
|
rc_sq_wqe->va =
|
||||||
|
cpu_to_le64(rdma_wr(wr)->remote_addr);
|
||||||
break;
|
break;
|
||||||
case IB_WR_RDMA_WRITE:
|
case IB_WR_RDMA_WRITE:
|
||||||
roce_set_field(rc_sq_wqe->byte_4,
|
roce_set_field(rc_sq_wqe->byte_4,
|
||||||
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
|
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
|
||||||
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
|
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
|
||||||
HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
|
HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
|
||||||
rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
|
rc_sq_wqe->rkey =
|
||||||
rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
|
cpu_to_le32(rdma_wr(wr)->rkey);
|
||||||
|
rc_sq_wqe->va =
|
||||||
|
cpu_to_le64(rdma_wr(wr)->remote_addr);
|
||||||
break;
|
break;
|
||||||
case IB_WR_RDMA_WRITE_WITH_IMM:
|
case IB_WR_RDMA_WRITE_WITH_IMM:
|
||||||
roce_set_field(rc_sq_wqe->byte_4,
|
roce_set_field(rc_sq_wqe->byte_4,
|
||||||
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
|
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
|
||||||
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
|
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
|
||||||
HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
|
HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
|
||||||
rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
|
rc_sq_wqe->rkey =
|
||||||
rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
|
cpu_to_le32(rdma_wr(wr)->rkey);
|
||||||
|
rc_sq_wqe->va =
|
||||||
|
cpu_to_le64(rdma_wr(wr)->remote_addr);
|
||||||
break;
|
break;
|
||||||
case IB_WR_SEND:
|
case IB_WR_SEND:
|
||||||
roce_set_field(rc_sq_wqe->byte_4,
|
roce_set_field(rc_sq_wqe->byte_4,
|
||||||
@ -209,70 +418,17 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
|||||||
|
|
||||||
wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
|
wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
|
||||||
dseg = wqe;
|
dseg = wqe;
|
||||||
if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
|
|
||||||
if (rc_sq_wqe->msg_len >
|
ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,
|
||||||
hr_dev->caps.max_sq_inline) {
|
&sge_ind, bad_wr);
|
||||||
ret = -EINVAL;
|
if (ret)
|
||||||
*bad_wr = wr;
|
|
||||||
dev_err(dev, "inline len(1-%d)=%d, illegal",
|
|
||||||
rc_sq_wqe->msg_len,
|
|
||||||
hr_dev->caps.max_sq_inline);
|
|
||||||
goto out;
|
goto out;
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < wr->num_sge; i++) {
|
|
||||||
memcpy(wqe, ((void *)wr->sg_list[i].addr),
|
|
||||||
wr->sg_list[i].length);
|
|
||||||
wqe += wr->sg_list[i].length;
|
|
||||||
wqe_sz += wr->sg_list[i].length;
|
|
||||||
}
|
|
||||||
|
|
||||||
roce_set_bit(rc_sq_wqe->byte_4,
|
|
||||||
V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1);
|
|
||||||
} else {
|
|
||||||
if (wr->num_sge <= 2) {
|
|
||||||
for (i = 0; i < wr->num_sge; i++) {
|
|
||||||
if (likely(wr->sg_list[i].length)) {
|
|
||||||
set_data_seg_v2(dseg,
|
|
||||||
wr->sg_list + i);
|
|
||||||
dseg++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
roce_set_field(rc_sq_wqe->byte_20,
|
|
||||||
V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
|
|
||||||
V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
|
|
||||||
sge_ind & (qp->sge.sge_cnt - 1));
|
|
||||||
|
|
||||||
for (i = 0; i < 2; i++) {
|
|
||||||
if (likely(wr->sg_list[i].length)) {
|
|
||||||
set_data_seg_v2(dseg,
|
|
||||||
wr->sg_list + i);
|
|
||||||
dseg++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
dseg = get_send_extend_sge(qp,
|
|
||||||
sge_ind & (qp->sge.sge_cnt - 1));
|
|
||||||
|
|
||||||
for (i = 0; i < wr->num_sge - 2; i++) {
|
|
||||||
if (likely(wr->sg_list[i + 2].length)) {
|
|
||||||
set_data_seg_v2(dseg,
|
|
||||||
wr->sg_list + 2 + i);
|
|
||||||
dseg++;
|
|
||||||
sge_ind++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
roce_set_field(rc_sq_wqe->byte_16,
|
|
||||||
V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
|
|
||||||
V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
|
|
||||||
wr->num_sge);
|
|
||||||
wqe_sz += wr->num_sge *
|
|
||||||
sizeof(struct hns_roce_v2_wqe_data_seg);
|
|
||||||
}
|
|
||||||
ind++;
|
ind++;
|
||||||
|
} else {
|
||||||
|
dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
|
||||||
|
spin_unlock_irqrestore(&qp->sq.lock, flags);
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
out:
|
out:
|
||||||
|
|||||||
@ -919,6 +919,90 @@ struct hns_roce_v2_cq_db {
|
|||||||
|
|
||||||
#define V2_CQ_DB_PARAMETER_NOTIFY_S 24
|
#define V2_CQ_DB_PARAMETER_NOTIFY_S 24
|
||||||
|
|
||||||
|
struct hns_roce_v2_ud_send_wqe {
|
||||||
|
u32 byte_4;
|
||||||
|
u32 msg_len;
|
||||||
|
u32 immtdata;
|
||||||
|
u32 byte_16;
|
||||||
|
u32 byte_20;
|
||||||
|
u32 byte_24;
|
||||||
|
u32 qkey;
|
||||||
|
u32 byte_32;
|
||||||
|
u32 byte_36;
|
||||||
|
u32 byte_40;
|
||||||
|
u32 dmac;
|
||||||
|
u32 byte_48;
|
||||||
|
u8 dgid[GID_LEN_V2];
|
||||||
|
|
||||||
|
};
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_4_SE_S 11
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_16_PD_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_SL_S 20
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_0_S 0
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_1_S 8
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_2_S 16
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_3_S 24
|
||||||
|
#define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
|
||||||
|
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
|
||||||
|
#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
|
||||||
|
|
||||||
struct hns_roce_v2_rc_send_wqe {
|
struct hns_roce_v2_rc_send_wqe {
|
||||||
u32 byte_4;
|
u32 byte_4;
|
||||||
u32 msg_len;
|
u32 msg_len;
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user