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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
ath10k: drop probe responses when too many are queued
In a noisy environment, when multiple interfaces are created, the management tx descriptors are fully occupied by the probe responses from all the interfaces. This prevents a new station from a successful association. Fix this by limiting the probe responses when the specified threshold limit is reached. Signed-off-by: Vivek Natarajan <nataraja@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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a925a37639
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7b7da0a021
@ -54,6 +54,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.has_shifted_cc_wraparound = true,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.fw = {
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.dir = QCA988X_HW_2_0_FW_DIR,
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.fw = QCA988X_HW_2_0_FW_FILE,
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@ -70,6 +71,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.uart_pin = 6,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.fw = {
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.dir = QCA6174_HW_2_1_FW_DIR,
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.fw = QCA6174_HW_2_1_FW_FILE,
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@ -86,6 +88,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.uart_pin = 6,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.fw = {
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.dir = QCA6174_HW_3_0_FW_DIR,
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.fw = QCA6174_HW_3_0_FW_FILE,
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@ -102,6 +105,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.uart_pin = 6,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.fw = {
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/* uses same binaries as hw3.0 */
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.dir = QCA6174_HW_3_0_FW_DIR,
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@ -120,6 +124,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0x00000700,
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.continuous_frag_desc = true,
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.channel_counters_freq_hz = 150000,
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.max_probe_resp_desc_thres = 24,
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.fw = {
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.dir = QCA99X0_HW_2_0_FW_DIR,
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.fw = QCA99X0_HW_2_0_FW_FILE,
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@ -612,6 +612,11 @@ struct ath10k {
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u32 channel_counters_freq_hz;
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/* Mgmt tx descriptors threshold for limiting probe response
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* frames.
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*/
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u32 max_probe_resp_desc_thres;
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struct ath10k_hw_params_fw {
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const char *dir;
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const char *fw;
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@ -1485,6 +1485,7 @@ struct ath10k_htt {
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spinlock_t tx_lock;
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int max_num_pending_tx;
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int num_pending_tx;
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int num_pending_mgmt_tx;
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struct idr pending_tx;
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wait_queue_head_t empty_tx_wq;
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struct dma_pool *tx_pool;
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@ -1587,7 +1588,7 @@ int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
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u8 max_subfrms_ampdu,
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u8 max_subfrms_amsdu);
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void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);
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void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc);
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int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
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void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
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int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *);
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@ -22,22 +22,28 @@
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#include "txrx.h"
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#include "debug.h"
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void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
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void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc)
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{
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if (limit_mgmt_desc)
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htt->num_pending_mgmt_tx--;
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htt->num_pending_tx--;
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if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
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ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
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}
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static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
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static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt,
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bool limit_mgmt_desc)
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{
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spin_lock_bh(&htt->tx_lock);
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__ath10k_htt_tx_dec_pending(htt);
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__ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
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spin_unlock_bh(&htt->tx_lock);
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}
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static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
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static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt,
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bool limit_mgmt_desc, bool is_probe_resp)
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{
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struct ath10k *ar = htt->ar;
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int ret = 0;
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spin_lock_bh(&htt->tx_lock);
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@ -47,6 +53,15 @@ static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
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goto exit;
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}
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if (limit_mgmt_desc) {
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if (is_probe_resp && (htt->num_pending_mgmt_tx >
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ar->hw_params.max_probe_resp_desc_thres)) {
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ret = -EBUSY;
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goto exit;
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}
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htt->num_pending_mgmt_tx++;
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}
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htt->num_pending_tx++;
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if (htt->num_pending_tx == htt->max_num_pending_tx)
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ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
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@ -417,8 +432,19 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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int len = 0;
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int msdu_id = -1;
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int res;
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struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
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bool limit_mgmt_desc = false;
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bool is_probe_resp = false;
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if (ar->hw_params.max_probe_resp_desc_thres) {
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limit_mgmt_desc = true;
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if (ieee80211_is_probe_resp(hdr->frame_control))
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is_probe_resp = true;
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}
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res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp);
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res = ath10k_htt_tx_inc_pending(htt);
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if (res)
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goto err;
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@ -476,7 +502,7 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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ath10k_htt_tx_free_msdu_id(htt, msdu_id);
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spin_unlock_bh(&htt->tx_lock);
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err_tx_dec:
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ath10k_htt_tx_dec_pending(htt);
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ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
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err:
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return res;
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}
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@ -498,8 +524,18 @@ int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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dma_addr_t paddr = 0;
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u32 frags_paddr = 0;
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struct htt_msdu_ext_desc *ext_desc = NULL;
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bool limit_mgmt_desc = false;
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bool is_probe_resp = false;
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res = ath10k_htt_tx_inc_pending(htt);
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if (unlikely(ieee80211_is_mgmt(hdr->frame_control)) &&
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ar->hw_params.max_probe_resp_desc_thres) {
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limit_mgmt_desc = true;
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if (ieee80211_is_probe_resp(hdr->frame_control))
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is_probe_resp = true;
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}
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res = ath10k_htt_tx_inc_pending(htt, limit_mgmt_desc, is_probe_resp);
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if (res)
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goto err;
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@ -678,7 +714,7 @@ int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
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ath10k_htt_tx_free_msdu_id(htt, msdu_id);
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spin_unlock_bh(&htt->tx_lock);
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err_tx_dec:
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ath10k_htt_tx_dec_pending(htt);
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ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
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err:
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return res;
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}
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@ -52,6 +52,9 @@ void ath10k_txrx_tx_unref(struct ath10k_htt *htt,
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struct ieee80211_tx_info *info;
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struct ath10k_skb_cb *skb_cb;
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struct sk_buff *msdu;
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struct ieee80211_hdr *hdr;
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__le16 fc;
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bool limit_mgmt_desc = false;
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ath10k_dbg(ar, ATH10K_DBG_HTT,
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"htt tx completion msdu_id %u discard %d no_ack %d success %d\n",
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@ -72,14 +75,21 @@ void ath10k_txrx_tx_unref(struct ath10k_htt *htt,
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spin_unlock_bh(&htt->tx_lock);
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return;
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}
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hdr = (struct ieee80211_hdr *)msdu->data;
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fc = hdr->frame_control;
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if (unlikely(ieee80211_is_mgmt(fc)) &&
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ar->hw_params.max_probe_resp_desc_thres)
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limit_mgmt_desc = true;
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ath10k_htt_tx_free_msdu_id(htt, tx_done->msdu_id);
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__ath10k_htt_tx_dec_pending(htt);
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__ath10k_htt_tx_dec_pending(htt, limit_mgmt_desc);
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if (htt->num_pending_tx == 0)
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wake_up(&htt->empty_tx_wq);
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spin_unlock_bh(&htt->tx_lock);
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skb_cb = ATH10K_SKB_CB(msdu);
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dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
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if (skb_cb->htt.txbuf)
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