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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 12:06:42 +07:00
OMAPDSS: DSI: separate LP clock info from dsi_clock_info
struct dsi_clock_info represents the clocks handled by the DSI, mostly PLL related clocks. In an effort to create common PLL code, we need to remove all the non-PLL items from dsi_clock_info. This patch removes LP clock related fields from dsi_clock_info, and creates a new struct dsi_lp_clock_info for holding clock info for the LP clock. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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1a7f4bf186
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@ -287,6 +287,11 @@ struct dsi_clk_calc_ctx {
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struct omap_dss_dsi_videomode_timings dsi_vm;
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};
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struct dsi_lp_clock_info {
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unsigned long lp_clk;
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u16 lp_clk_div;
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};
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struct dsi_data {
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struct platform_device *pdev;
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void __iomem *proto_base;
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@ -307,6 +312,9 @@ struct dsi_data {
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struct dsi_clock_info current_cinfo;
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struct dsi_lp_clock_info user_lp_cinfo;
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struct dsi_lp_clock_info current_lp_cinfo;
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bool vdds_dsi_enabled;
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struct regulator *vdds_dsi_reg;
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@ -1293,10 +1301,10 @@ static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
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return r;
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}
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static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
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unsigned long lp_clk_min, unsigned long lp_clk_max)
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static int dsi_lp_clock_calc(unsigned long dsi_fclk,
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unsigned long lp_clk_min, unsigned long lp_clk_max,
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struct dsi_lp_clock_info *lp_cinfo)
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{
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unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
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unsigned lp_clk_div;
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unsigned long lp_clk;
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@ -1306,8 +1314,8 @@ static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
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if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
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return -EINVAL;
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cinfo->lp_clk_div = lp_clk_div;
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cinfo->lp_clk = lp_clk;
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lp_cinfo->lp_clk_div = lp_clk_div;
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lp_cinfo->lp_clk = lp_clk;
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return 0;
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}
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@ -1319,7 +1327,7 @@ static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
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unsigned lp_clk_div;
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unsigned long lp_clk;
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lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
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lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
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if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
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return -EINVAL;
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@ -1329,8 +1337,8 @@ static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
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lp_clk = dsi_fclk / 2 / lp_clk_div;
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DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
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dsi->current_cinfo.lp_clk = lp_clk;
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dsi->current_cinfo.lp_clk_div = lp_clk_div;
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dsi->current_lp_cinfo.lp_clk = lp_clk;
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dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
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/* LP_CLK_DIVISOR */
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REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
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@ -1801,7 +1809,7 @@ static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
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seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
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seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
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seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
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dsi_runtime_put(dsidev);
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}
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@ -5110,8 +5118,8 @@ static int dsi_set_config(struct omap_dss_device *dssdev,
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dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
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r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
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config->lp_clk_max);
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r = dsi_lp_clock_calc(ctx.dsi_cinfo.dsi_pll_hsdiv_dsi_clk,
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config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
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if (r) {
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DSSERR("failed to find suitable DSI LP clock settings\n");
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goto err;
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@ -119,7 +119,6 @@ struct dsi_clock_info {
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* OMAP4: PLLx_CLK1 */
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unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
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* OMAP4: PLLx_CLK2 */
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unsigned long lp_clk;
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/* dividers */
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u16 regn;
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@ -128,7 +127,6 @@ struct dsi_clock_info {
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* OMAP4: REGM4 */
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u16 regm_dsi; /* OMAP3: REGM4
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* OMAP4: REGM5 */
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u16 lp_clk_div;
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};
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struct dss_lcd_mgr_config {
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