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clk: rockchip: include downstream muxes into fractional dividers on rk3368
During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Elaine Zhang
Heiko Stuebner
parent
bdc7deec2f
commit
7af8a26ce7
@ -243,6 +243,34 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
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RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
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};
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static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
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MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
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MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
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MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
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MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
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MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
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MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
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MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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/*
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* Clock-Architecture Diagram 2
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@ -339,11 +367,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
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RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(6), 1, GFLAGS),
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COMPOSITE_FRAC(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(28), 0,
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RK3368_CLKGATE_CON(6), 2, GFLAGS),
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MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(27), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(28), 0,
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RK3368_CLKGATE_CON(6), 2, GFLAGS,
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&rk3368_i2s_8ch_fracmux),
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COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
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RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
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RK3368_CLKGATE_CON(6), 0, GFLAGS),
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@ -352,21 +379,21 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
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RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(6), 4, GFLAGS),
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COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(32), 0,
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RK3368_CLKGATE_CON(6), 5, GFLAGS),
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COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
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RK3368_CLKGATE_CON(6), 6, GFLAGS),
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COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(32), 0,
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RK3368_CLKGATE_CON(6), 5, GFLAGS,
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&rk3368_spdif_8ch_fracmux),
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GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
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RK3368_CLKGATE_CON(6), 6, GFLAGS),
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COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
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RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(5), 13, GFLAGS),
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COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(54), 0,
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RK3368_CLKGATE_CON(5), 14, GFLAGS),
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COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
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RK3368_CLKGATE_CON(5), 15, GFLAGS),
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COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(54), 0,
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RK3368_CLKGATE_CON(5), 14, GFLAGS,
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&rk3368_i2s_2ch_fracmux),
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GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
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RK3368_CLKGATE_CON(5), 15, GFLAGS),
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COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
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RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
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@ -562,38 +589,34 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
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RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(2), 0, GFLAGS),
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COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(34), 0,
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RK3368_CLKGATE_CON(2), 1, GFLAGS),
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MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(33), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(34), 0,
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RK3368_CLKGATE_CON(2), 1, GFLAGS,
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&rk3368_uart0_fracmux),
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COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
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RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(2), 2, GFLAGS),
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COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(36), 0,
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RK3368_CLKGATE_CON(2), 3, GFLAGS),
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MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(35), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(36), 0,
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RK3368_CLKGATE_CON(2), 3, GFLAGS,
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&rk3368_uart1_fracmux),
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COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
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RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(2), 6, GFLAGS),
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COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(40), 0,
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RK3368_CLKGATE_CON(2), 7, GFLAGS),
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MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(39), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(40), 0,
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RK3368_CLKGATE_CON(2), 7, GFLAGS,
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&rk3368_uart3_fracmux),
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COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
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RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
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RK3368_CLKGATE_CON(2), 8, GFLAGS),
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COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(42), 0,
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RK3368_CLKGATE_CON(2), 9, GFLAGS),
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MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(41), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
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RK3368_CLKSEL_CON(42), 0,
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RK3368_CLKGATE_CON(2), 9, GFLAGS,
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&rk3368_uart4_fracmux),
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COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
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RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
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