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ARM: OMAP2+: Drop legacy platform data for cpsw on am3 and am4
We can now probe cpsw with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property for am3 and am4. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Cc: Keerthy <j-keerthy@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -673,7 +673,6 @@ segment@0 { /* 0x4a000000 */
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target-module@100000 { /* 0x4a100000, ap 3 08.0 */
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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ti,hwmods = "cpgmac0";
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reg = <0x101200 0x4>,
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<0x101208 0x4>,
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<0x101204 0x4>;
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@ -723,7 +722,6 @@ davinci_mdio: mdio@1000 {
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "davinci_mdio";
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bus_freq = <1000000>;
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reg = <0x1000 0x100>;
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status = "disabled";
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@ -512,7 +512,6 @@ segment@0 { /* 0x4a000000 */
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target-module@100000 { /* 0x4a100000, ap 3 04.0 */
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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ti,hwmods = "cpgmac0";
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reg = <0x101200 0x4>,
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<0x101208 0x4>,
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<0x101204 0x4>;
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@ -563,7 +562,6 @@ davinci_mdio: mdio@1000 {
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "davinci_mdio";
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bus_freq = <1000000>;
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status = "disabled";
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};
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@ -30,7 +30,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
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extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
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extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
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extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
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extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
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extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
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extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
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extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
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@ -72,8 +71,6 @@ extern struct omap_hwmod am33xx_rng_hwmod;
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extern struct omap_hwmod am33xx_ocmcram_hwmod;
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extern struct omap_hwmod am33xx_smartreflex0_hwmod;
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extern struct omap_hwmod am33xx_smartreflex1_hwmod;
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extern struct omap_hwmod am33xx_cpgmac0_hwmod;
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extern struct omap_hwmod am33xx_mdio_hwmod;
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extern struct omap_hwmod am33xx_dcan0_hwmod;
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extern struct omap_hwmod am33xx_dcan1_hwmod;
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extern struct omap_hwmod am33xx_elm_hwmod;
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@ -122,12 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
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.master = &am33xx_cpgmac0_hwmod,
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.slave = &am33xx_mdio_hwmod,
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.user = OCP_USER_MPU,
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};
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struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
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.master = &am33xx_l4_ls_hwmod,
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.slave = &am33xx_elm_hwmod,
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@ -349,54 +349,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = {
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.name = "control",
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};
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/*
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* 'cpgmac' class
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* cpsw/cpgmac sub system
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*/
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static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x8,
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.syss_offs = 0x4,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
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MSTANDBY_NO),
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.sysc_fields = &omap_hwmod_sysc_type3,
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};
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static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
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.name = "cpgmac0",
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.sysc = &am33xx_cpgmac_sysc,
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};
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struct omap_hwmod am33xx_cpgmac0_hwmod = {
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.name = "cpgmac0",
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.class = &am33xx_cpgmac0_hwmod_class,
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.clkdm_name = "cpsw_125mhz_clkdm",
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.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
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.main_clk = "cpsw_125mhz_gclk",
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.mpu_rt_idx = 1,
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* mdio class
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*/
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static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
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.name = "davinci_mdio",
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};
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struct omap_hwmod am33xx_mdio_hwmod = {
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.name = "davinci_mdio",
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.class = &am33xx_mdio_hwmod_class,
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.clkdm_name = "cpsw_125mhz_clkdm",
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.main_clk = "cpsw_125mhz_gclk",
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};
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/*
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* dcan class
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*/
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@ -1072,7 +1024,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
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CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
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@ -1134,7 +1085,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
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CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
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@ -372,13 +372,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
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.master = &am33xx_l4_hs_hwmod,
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.slave = &am33xx_cpgmac0_hwmod,
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.clk = "cpsw_125mhz_gclk",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_lcdc_hwmod,
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@ -462,8 +455,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l3_main__tptc2,
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&am33xx_l3_main__ocmc,
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&am33xx_l3_s__usbss,
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&am33xx_l4_hs__cpgmac0,
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&am33xx_cpgmac0__mdio,
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&am33xx_l3_main__sha0,
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&am33xx_l3_main__aes0,
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&am33xx_l4_per__rng,
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@ -597,13 +597,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
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.master = &am43xx_l4_hs_hwmod,
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.slave = &am33xx_cpgmac0_hwmod,
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.clk = "cpsw_125mhz_gclk",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_timer1_hwmod,
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@ -859,8 +852,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l3_main__tptc1,
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&am33xx_l3_main__tptc2,
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&am33xx_l3_main__ocmc,
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&am43xx_l4_hs__cpgmac0,
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&am33xx_cpgmac0__mdio,
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&am33xx_l3_main__sha0,
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&am33xx_l3_main__aes0,
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&am43xx_l3_main__des,
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