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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: Change watermark hook calling convention
Just pass the atomic_state+crtc to the watermarks hooks. Eeasier time for the caller when it doesn't have to think what to pass. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191118164430.27265-7-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
parent
5b4f4e94df
commit
7a8fdb1f27
@ -6189,9 +6189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
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* we'll continue to update watermarks the old way, if flags tell
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* us to.
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*/
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if (dev_priv->display.initial_watermarks != NULL)
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dev_priv->display.initial_watermarks(intel_state,
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pipe_config);
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if (dev_priv->display.initial_watermarks)
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dev_priv->display.initial_watermarks(intel_state, crtc);
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else if (pipe_config->update_wm_pre)
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intel_update_watermarks(crtc);
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}
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@ -6539,8 +6538,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
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/* update DSPCNTR to configure gamma for pipe bottom color */
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intel_disable_primary_plane(pipe_config);
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if (dev_priv->display.initial_watermarks != NULL)
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dev_priv->display.initial_watermarks(state, pipe_config);
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if (dev_priv->display.initial_watermarks)
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dev_priv->display.initial_watermarks(state, intel_crtc);
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intel_enable_pipe(pipe_config);
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if (pipe_config->has_pch_encoder)
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@ -6698,8 +6697,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
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if (!transcoder_is_dsi(cpu_transcoder))
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intel_ddi_enable_transcoder_func(pipe_config);
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if (dev_priv->display.initial_watermarks != NULL)
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dev_priv->display.initial_watermarks(state, pipe_config);
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if (dev_priv->display.initial_watermarks)
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dev_priv->display.initial_watermarks(state, intel_crtc);
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if (INTEL_GEN(dev_priv) >= 11)
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icl_pipe_mbus_enable(intel_crtc);
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@ -7083,7 +7082,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
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/* update DSPCNTR to configure gamma for pipe bottom color */
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intel_disable_primary_plane(pipe_config);
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dev_priv->display.initial_watermarks(state, pipe_config);
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dev_priv->display.initial_watermarks(state, intel_crtc);
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intel_enable_pipe(pipe_config);
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intel_crtc_vblank_on(pipe_config);
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@ -7138,9 +7137,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
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/* update DSPCNTR to configure gamma for pipe bottom color */
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intel_disable_primary_plane(pipe_config);
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if (dev_priv->display.initial_watermarks != NULL)
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dev_priv->display.initial_watermarks(state,
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pipe_config);
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if (dev_priv->display.initial_watermarks)
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dev_priv->display.initial_watermarks(state, intel_crtc);
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else
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intel_update_watermarks(intel_crtc);
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intel_enable_pipe(pipe_config);
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@ -14321,6 +14319,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
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struct intel_crtc_state *old_crtc_state,
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struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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bool modeset = needs_modeset(new_crtc_state);
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@ -14344,8 +14343,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
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}
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if (dev_priv->display.atomic_update_watermarks)
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dev_priv->display.atomic_update_watermarks(state,
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new_crtc_state);
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dev_priv->display.atomic_update_watermarks(state, crtc);
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}
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static void intel_update_crtc(struct intel_crtc *crtc,
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@ -14449,8 +14447,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
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if (!new_crtc_state->hw.active &&
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!HAS_GMCH(dev_priv) &&
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dev_priv->display.initial_watermarks)
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dev_priv->display.initial_watermarks(state,
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new_crtc_state);
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dev_priv->display.initial_watermarks(state, crtc);
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}
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static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
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@ -14900,8 +14897,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
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*/
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for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
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if (dev_priv->display.optimize_watermarks)
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dev_priv->display.optimize_watermarks(state,
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new_crtc_state);
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dev_priv->display.optimize_watermarks(state, crtc);
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}
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for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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@ -16856,7 +16852,7 @@ static void sanitize_watermarks(struct drm_device *dev)
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/* Write calculated watermark values back */
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for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
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crtc_state->wm.need_postvbl_update = true;
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dev_priv->display.optimize_watermarks(intel_state, crtc_state);
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dev_priv->display.optimize_watermarks(intel_state, crtc);
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to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
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}
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@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
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int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
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int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
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void (*initial_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state);
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struct intel_crtc *crtc);
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void (*atomic_update_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state);
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struct intel_crtc *crtc);
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void (*optimize_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state);
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struct intel_crtc *crtc);
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int (*compute_global_watermarks)(struct intel_atomic_state *state);
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void (*update_wm)(struct intel_crtc *crtc);
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int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
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@ -1528,10 +1528,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
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}
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static void g4x_initial_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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mutex_lock(&dev_priv->wm.wm_mutex);
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crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
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@ -1540,10 +1541,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
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}
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static void g4x_optimize_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!crtc_state->wm.need_postvbl_update)
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return;
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@ -1923,11 +1925,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
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(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
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static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_uncore *uncore = &dev_priv->uncore;
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct vlv_fifo_state *fifo_state =
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&crtc_state->wm.vlv.fifo_state;
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int sprite0_start, sprite1_start, fifo_size;
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@ -2147,10 +2150,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
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}
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static void vlv_initial_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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mutex_lock(&dev_priv->wm.wm_mutex);
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crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
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@ -2159,10 +2163,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
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}
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static void vlv_optimize_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!crtc_state->wm.need_postvbl_update)
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return;
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@ -5499,11 +5504,12 @@ skl_compute_wm(struct intel_atomic_state *state)
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}
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static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
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enum pipe pipe = crtc->pipe;
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if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
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@ -5513,10 +5519,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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}
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static void skl_initial_wm(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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struct skl_ddb_values *results = &state->wm_results;
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if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
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@ -5525,7 +5532,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
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mutex_lock(&dev_priv->wm.wm_mutex);
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if (crtc_state->uapi.active_changed)
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skl_atomic_update_crtc_wm(state, crtc_state);
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skl_atomic_update_crtc_wm(state, crtc);
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mutex_unlock(&dev_priv->wm.wm_mutex);
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}
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@ -5581,10 +5588,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
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}
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static void ilk_initial_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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mutex_lock(&dev_priv->wm.wm_mutex);
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crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
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@ -5593,10 +5601,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
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}
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static void ilk_optimize_watermarks(struct intel_atomic_state *state,
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struct intel_crtc_state *crtc_state)
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struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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if (!crtc_state->wm.need_postvbl_update)
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return;
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