mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:48:56 +07:00
drm/i915/selftests: Add tiled blits selftest
Extend coverage of the blitter client by exercising conversion to and from tiled sources. In the process we perform spot checks to verify that the tiling/detiling is being applied correctly, along with position invariance of the tiling parameters. Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200430064957.14942-1-chris@chris-wilson.co.uk
This commit is contained in:
Zbigniew Kempczyński
Chris Wilson
parent
de3b4d9361
commit
79eb8c7f01
@ -7,9 +7,12 @@
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#include "gt/intel_engine_user.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gpu_commands.h"
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#include "gem/i915_gem_lmem.h"
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#include "selftests/igt_flush_test.h"
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#include "selftests/mock_drm.h"
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#include "selftests/i915_random.h"
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#include "huge_gem_object.h"
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#include "mock_context.h"
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@ -127,10 +130,602 @@ static int igt_client_fill(void *arg)
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} while (1);
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}
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#define WIDTH 512
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#define HEIGHT 32
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struct blit_buffer {
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struct i915_vma *vma;
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u32 start_val;
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u32 tiling;
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};
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struct tiled_blits {
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struct intel_context *ce;
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struct blit_buffer buffers[3];
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struct blit_buffer scratch;
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struct i915_vma *batch;
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u64 hole;
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u32 width;
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u32 height;
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};
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static int prepare_blit(const struct tiled_blits *t,
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struct blit_buffer *dst,
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struct blit_buffer *src,
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struct drm_i915_gem_object *batch)
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{
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const int gen = INTEL_GEN(to_i915(batch->base.dev));
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bool use_64b_reloc = gen >= 8;
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u32 src_pitch, dst_pitch;
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u32 cmd, *cs;
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cs = i915_gem_object_pin_map(batch, I915_MAP_WC);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
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cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
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if (src->tiling == I915_TILING_Y)
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cmd |= BCS_SRC_Y;
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if (dst->tiling == I915_TILING_Y)
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cmd |= BCS_DST_Y;
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*cs++ = cmd;
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cmd = MI_FLUSH_DW;
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if (gen >= 8)
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cmd++;
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*cs++ = cmd;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
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if (gen >= 8)
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cmd += 2;
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src_pitch = t->width * 4;
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if (src->tiling) {
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cmd |= XY_SRC_COPY_BLT_SRC_TILED;
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src_pitch /= 4;
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}
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dst_pitch = t->width * 4;
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if (dst->tiling) {
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cmd |= XY_SRC_COPY_BLT_DST_TILED;
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dst_pitch /= 4;
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}
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*cs++ = cmd;
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*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
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*cs++ = 0;
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*cs++ = t->height << 16 | t->width;
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*cs++ = lower_32_bits(dst->vma->node.start);
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if (use_64b_reloc)
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*cs++ = upper_32_bits(dst->vma->node.start);
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*cs++ = 0;
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*cs++ = src_pitch;
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*cs++ = lower_32_bits(src->vma->node.start);
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if (use_64b_reloc)
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*cs++ = upper_32_bits(src->vma->node.start);
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*cs++ = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(batch);
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i915_gem_object_unpin_map(batch);
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return 0;
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}
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static void tiled_blits_destroy_buffers(struct tiled_blits *t)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(t->buffers); i++)
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i915_vma_put(t->buffers[i].vma);
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i915_vma_put(t->scratch.vma);
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i915_vma_put(t->batch);
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}
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static struct i915_vma *
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__create_vma(struct tiled_blits *t, size_t size, bool lmem)
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{
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struct drm_i915_private *i915 = t->ce->vm->i915;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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if (lmem)
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obj = i915_gem_object_create_lmem(i915, size, 0);
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else
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obj = i915_gem_object_create_shmem(i915, size);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vma = i915_vma_instance(obj, t->ce->vm, NULL);
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if (IS_ERR(vma))
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i915_gem_object_put(obj);
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return vma;
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}
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static struct i915_vma *create_vma(struct tiled_blits *t, bool lmem)
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{
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return __create_vma(t, PAGE_ALIGN(t->width * t->height * 4), lmem);
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}
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static int tiled_blits_create_buffers(struct tiled_blits *t,
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int width, int height,
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struct rnd_state *prng)
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{
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struct drm_i915_private *i915 = t->ce->engine->i915;
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int i;
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t->width = width;
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t->height = height;
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t->batch = __create_vma(t, PAGE_SIZE, false);
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if (IS_ERR(t->batch))
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return PTR_ERR(t->batch);
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t->scratch.vma = create_vma(t, false);
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if (IS_ERR(t->scratch.vma)) {
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i915_vma_put(t->batch);
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return PTR_ERR(t->scratch.vma);
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}
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for (i = 0; i < ARRAY_SIZE(t->buffers); i++) {
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struct i915_vma *vma;
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vma = create_vma(t, HAS_LMEM(i915) && i % 2);
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if (IS_ERR(vma)) {
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tiled_blits_destroy_buffers(t);
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return PTR_ERR(vma);
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}
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t->buffers[i].vma = vma;
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t->buffers[i].tiling =
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i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
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}
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return 0;
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}
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static void fill_scratch(struct tiled_blits *t, u32 *vaddr, u32 val)
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{
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int i;
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t->scratch.start_val = val;
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for (i = 0; i < t->width * t->height; i++)
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vaddr[i] = val++;
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i915_gem_object_flush_map(t->scratch.vma->obj);
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}
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static void hexdump(const void *buf, size_t len)
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{
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const size_t rowsize = 8 * sizeof(u32);
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const void *prev = NULL;
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bool skip = false;
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size_t pos;
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for (pos = 0; pos < len; pos += rowsize) {
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char line[128];
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if (prev && !memcmp(prev, buf + pos, rowsize)) {
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if (!skip) {
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pr_info("*\n");
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skip = true;
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}
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continue;
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}
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WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
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rowsize, sizeof(u32),
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line, sizeof(line),
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false) >= sizeof(line));
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pr_info("[%04zx] %s\n", pos, line);
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prev = buf + pos;
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skip = false;
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}
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}
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static u64 swizzle_bit(unsigned int bit, u64 offset)
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{
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return (offset & BIT_ULL(bit)) >> (bit - 6);
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}
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static u64 tiled_offset(const struct intel_gt *gt,
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u64 v,
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unsigned int stride,
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unsigned int tiling)
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{
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unsigned int swizzle;
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u64 x, y;
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if (tiling == I915_TILING_NONE)
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return v;
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y = div64_u64_rem(v, stride, &x);
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if (tiling == I915_TILING_X) {
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v = div64_u64_rem(y, 8, &y) * stride * 8;
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v += y * 512;
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v += div64_u64_rem(x, 512, &x) << 12;
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v += x;
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swizzle = gt->ggtt->bit_6_swizzle_x;
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} else {
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const unsigned int ytile_span = 16;
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const unsigned int ytile_height = 512;
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v = div64_u64_rem(y, 32, &y) * stride * 32;
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v += y * ytile_span;
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v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
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v += x;
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swizzle = gt->ggtt->bit_6_swizzle_y;
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}
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switch (swizzle) {
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case I915_BIT_6_SWIZZLE_9:
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v ^= swizzle_bit(9, v);
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break;
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case I915_BIT_6_SWIZZLE_9_10:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
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break;
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case I915_BIT_6_SWIZZLE_9_11:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
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break;
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case I915_BIT_6_SWIZZLE_9_10_11:
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v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
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break;
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}
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return v;
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}
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static const char *repr_tiling(int tiling)
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{
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switch (tiling) {
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case I915_TILING_NONE: return "linear";
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case I915_TILING_X: return "X";
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case I915_TILING_Y: return "Y";
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default: return "unknown";
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}
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}
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static int verify_buffer(const struct tiled_blits *t,
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struct blit_buffer *buf,
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struct rnd_state *prng)
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{
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const u32 *vaddr;
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int ret = 0;
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int x, y, p;
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x = i915_prandom_u32_max_state(t->width, prng);
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y = i915_prandom_u32_max_state(t->height, prng);
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p = y * t->width + x;
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vaddr = i915_gem_object_pin_map(buf->vma->obj, I915_MAP_WC);
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if (IS_ERR(vaddr))
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return PTR_ERR(vaddr);
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if (vaddr[0] != buf->start_val) {
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ret = -EINVAL;
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} else {
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u64 v = tiled_offset(buf->vma->vm->gt,
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p * 4, t->width * 4,
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buf->tiling);
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if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
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ret = -EINVAL;
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}
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if (ret) {
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pr_err("Invalid %s tiling detected at (%d, %d), start_val %x\n",
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repr_tiling(buf->tiling),
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x, y, buf->start_val);
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hexdump(vaddr, 4096);
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}
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i915_gem_object_unpin_map(buf->vma->obj);
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return ret;
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}
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static int move_to_active(struct i915_vma *vma,
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struct i915_request *rq,
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unsigned int flags)
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{
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int err;
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, false);
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if (err == 0)
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err = i915_vma_move_to_active(vma, rq, flags);
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i915_vma_unlock(vma);
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return err;
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}
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static int pin_buffer(struct i915_vma *vma, u64 addr)
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{
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int err;
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if (drm_mm_node_allocated(&vma->node) && vma->node.start != addr) {
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err = i915_vma_unbind(vma);
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if (err)
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return err;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_OFFSET_FIXED | addr);
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if (err)
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return err;
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return 0;
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}
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static int
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tiled_blit(struct tiled_blits *t,
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struct blit_buffer *dst, u64 dst_addr,
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struct blit_buffer *src, u64 src_addr)
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{
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struct i915_request *rq;
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int err;
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err = pin_buffer(src->vma, src_addr);
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if (err) {
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pr_err("Cannot pin src @ %llx\n", src_addr);
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return err;
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}
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err = pin_buffer(dst->vma, dst_addr);
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if (err) {
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pr_err("Cannot pin dst @ %llx\n", dst_addr);
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goto err_src;
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}
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err = i915_vma_pin(t->batch, 0, 0, PIN_USER | PIN_HIGH);
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if (err) {
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pr_err("cannot pin batch\n");
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goto err_dst;
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}
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err = prepare_blit(t, dst, src, t->batch->obj);
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if (err)
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goto err_bb;
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rq = intel_context_create_request(t->ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto err_bb;
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}
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err = move_to_active(t->batch, rq, 0);
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if (!err)
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err = move_to_active(src->vma, rq, 0);
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if (!err)
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err = move_to_active(dst->vma, rq, 0);
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if (!err)
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err = rq->engine->emit_bb_start(rq,
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t->batch->node.start,
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t->batch->node.size,
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0);
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i915_request_get(rq);
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i915_request_add(rq);
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if (i915_request_wait(rq, 0, HZ / 2) < 0)
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err = -ETIME;
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i915_request_put(rq);
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dst->start_val = src->start_val;
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err_bb:
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i915_vma_unpin(t->batch);
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err_dst:
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i915_vma_unpin(dst->vma);
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err_src:
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i915_vma_unpin(src->vma);
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return err;
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}
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static struct tiled_blits *
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tiled_blits_create(struct intel_engine_cs *engine, struct rnd_state *prng)
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{
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struct drm_mm_node hole;
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struct tiled_blits *t;
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u64 hole_size;
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int err;
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t = kzalloc(sizeof(*t), GFP_KERNEL);
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if (!t)
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return ERR_PTR(-ENOMEM);
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t->ce = intel_context_create(engine);
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if (IS_ERR(t->ce)) {
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err = PTR_ERR(t->ce);
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goto err_free;
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}
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hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
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hole_size *= 2; /* room to maneuver */
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hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
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mutex_lock(&t->ce->vm->mutex);
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memset(&hole, 0, sizeof(hole));
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err = drm_mm_insert_node_in_range(&t->ce->vm->mm, &hole,
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hole_size, 0, I915_COLOR_UNEVICTABLE,
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0, U64_MAX,
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DRM_MM_INSERT_BEST);
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if (!err)
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drm_mm_remove_node(&hole);
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mutex_unlock(&t->ce->vm->mutex);
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if (err) {
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err = -ENODEV;
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goto err_put;
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}
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t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
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pr_info("Using hole at %llx\n", t->hole);
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err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
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if (err)
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goto err_put;
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return t;
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err_put:
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intel_context_put(t->ce);
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err_free:
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kfree(t);
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return ERR_PTR(err);
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}
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static void tiled_blits_destroy(struct tiled_blits *t)
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{
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tiled_blits_destroy_buffers(t);
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intel_context_put(t->ce);
|
||||
kfree(t);
|
||||
}
|
||||
|
||||
static int tiled_blits_prepare(struct tiled_blits *t,
|
||||
struct rnd_state *prng)
|
||||
{
|
||||
u64 offset = PAGE_ALIGN(t->width * t->height * 4);
|
||||
u32 *map;
|
||||
int err;
|
||||
int i;
|
||||
|
||||
map = i915_gem_object_pin_map(t->scratch.vma->obj, I915_MAP_WC);
|
||||
if (IS_ERR(map))
|
||||
return PTR_ERR(map);
|
||||
|
||||
/* Use scratch to fill objects */
|
||||
for (i = 0; i < ARRAY_SIZE(t->buffers); i++) {
|
||||
fill_scratch(t, map, prandom_u32_state(prng));
|
||||
GEM_BUG_ON(verify_buffer(t, &t->scratch, prng));
|
||||
|
||||
err = tiled_blit(t,
|
||||
&t->buffers[i], t->hole + offset,
|
||||
&t->scratch, t->hole);
|
||||
if (err == 0)
|
||||
err = verify_buffer(t, &t->buffers[i], prng);
|
||||
if (err) {
|
||||
pr_err("Failed to create buffer %d\n", i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
i915_gem_object_unpin_map(t->scratch.vma->obj);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
|
||||
{
|
||||
u64 offset =
|
||||
round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
|
||||
int err;
|
||||
|
||||
/* We want to check position invariant tiling across GTT eviction */
|
||||
|
||||
err = tiled_blit(t,
|
||||
&t->buffers[1], t->hole + offset / 2,
|
||||
&t->buffers[0], t->hole + 2 * offset);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Reposition so that we overlap the old addresses, and slightly off */
|
||||
err = tiled_blit(t,
|
||||
&t->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
|
||||
&t->buffers[1], t->hole + 3 * offset / 2);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = verify_buffer(t, &t->buffers[2], prng);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __igt_client_tiled_blits(struct intel_engine_cs *engine,
|
||||
struct rnd_state *prng)
|
||||
{
|
||||
struct tiled_blits *t;
|
||||
int err;
|
||||
|
||||
t = tiled_blits_create(engine, prng);
|
||||
if (IS_ERR(t))
|
||||
return PTR_ERR(t);
|
||||
|
||||
err = tiled_blits_prepare(t, prng);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
err = tiled_blits_bounce(t, prng);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
out:
|
||||
tiled_blits_destroy(t);
|
||||
return err;
|
||||
}
|
||||
|
||||
static bool has_bit17_swizzle(int sw)
|
||||
{
|
||||
return (sw == I915_BIT_6_SWIZZLE_9_10_17 ||
|
||||
sw == I915_BIT_6_SWIZZLE_9_17);
|
||||
}
|
||||
|
||||
static bool bad_swizzling(struct drm_i915_private *i915)
|
||||
{
|
||||
struct i915_ggtt *ggtt = &i915->ggtt;
|
||||
|
||||
if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
||||
return true;
|
||||
|
||||
if (has_bit17_swizzle(ggtt->bit_6_swizzle_x) ||
|
||||
has_bit17_swizzle(ggtt->bit_6_swizzle_y))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int igt_client_tiled_blits(void *arg)
|
||||
{
|
||||
struct drm_i915_private *i915 = arg;
|
||||
I915_RND_STATE(prng);
|
||||
int inst = 0;
|
||||
|
||||
/* Test requires explicit BLT tiling controls */
|
||||
if (INTEL_GEN(i915) < 4)
|
||||
return 0;
|
||||
|
||||
if (bad_swizzling(i915)) /* Requires sane (sub-page) swizzling */
|
||||
return 0;
|
||||
|
||||
do {
|
||||
struct intel_engine_cs *engine;
|
||||
int err;
|
||||
|
||||
engine = intel_engine_lookup_user(i915,
|
||||
I915_ENGINE_CLASS_COPY,
|
||||
inst++);
|
||||
if (!engine)
|
||||
return 0;
|
||||
|
||||
err = __igt_client_tiled_blits(engine, &prng);
|
||||
if (err == -ENODEV)
|
||||
err = 0;
|
||||
if (err)
|
||||
return err;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915)
|
||||
{
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(igt_client_fill),
|
||||
SUBTEST(igt_client_tiled_blits),
|
||||
};
|
||||
|
||||
if (intel_gt_is_wedged(&i915->gt))
|
||||
|
||||
@ -561,6 +561,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
||||
* Registers used only by the command parser
|
||||
*/
|
||||
#define BCS_SWCTRL _MMIO(0x22200)
|
||||
#define BCS_SRC_Y REG_BIT(0)
|
||||
#define BCS_DST_Y REG_BIT(1)
|
||||
|
||||
/* There are 16 GPR registers */
|
||||
#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user