mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 09:16:39 +07:00
e1000e: initial support for i219
i219 is the next-generation LOM that will be available on systems with the Sunrise Point Platform Controller Hub (PCH) chipset from Intel. This patch provides the initial support for the device. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Tested-by: Carmen Edwards <carmenx.edwards@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
5e3d31896b
commit
79849ebc0e
@ -141,6 +141,7 @@
|
||||
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
|
||||
#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
|
||||
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
|
||||
#define E1000_RCTL_RDMTS_HEX 0x00010000
|
||||
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
|
||||
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
|
||||
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
|
||||
|
@ -132,6 +132,7 @@ enum e1000_boards {
|
||||
board_pchlan,
|
||||
board_pch2lan,
|
||||
board_pch_lpt,
|
||||
board_pch_spt
|
||||
};
|
||||
|
||||
struct e1000_ps_page {
|
||||
@ -501,6 +502,7 @@ extern const struct e1000_info e1000_ich10_info;
|
||||
extern const struct e1000_info e1000_pch_info;
|
||||
extern const struct e1000_info e1000_pch2_info;
|
||||
extern const struct e1000_info e1000_pch_lpt_info;
|
||||
extern const struct e1000_info e1000_pch_spt_info;
|
||||
extern const struct e1000_info e1000_es2_info;
|
||||
|
||||
void e1000e_ptp_init(struct e1000_adapter *adapter);
|
||||
|
@ -896,18 +896,20 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
|
||||
case e1000_pchlan:
|
||||
case e1000_pch2lan:
|
||||
case e1000_pch_lpt:
|
||||
case e1000_pch_spt:
|
||||
mask |= (1 << 18);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (mac->type == e1000_pch_lpt)
|
||||
if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt))
|
||||
wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >>
|
||||
E1000_FWSM_WLOCK_MAC_SHIFT;
|
||||
|
||||
for (i = 0; i < mac->rar_entry_count; i++) {
|
||||
if (mac->type == e1000_pch_lpt) {
|
||||
if ((mac->type == e1000_pch_lpt) ||
|
||||
(mac->type == e1000_pch_spt)) {
|
||||
/* Cannot test write-protected SHRAL[n] registers */
|
||||
if ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac)))
|
||||
continue;
|
||||
|
@ -87,6 +87,10 @@ struct e1000_hw;
|
||||
#define E1000_DEV_ID_PCH_I218_V2 0x15A1
|
||||
#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
|
||||
#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
|
||||
|
||||
#define E1000_REVISION_4 4
|
||||
|
||||
@ -108,6 +112,7 @@ enum e1000_mac_type {
|
||||
e1000_pchlan,
|
||||
e1000_pch2lan,
|
||||
e1000_pch_lpt,
|
||||
e1000_pch_spt,
|
||||
};
|
||||
|
||||
enum e1000_media_type {
|
||||
@ -153,6 +158,7 @@ enum e1000_bus_width {
|
||||
e1000_bus_width_pcie_x1,
|
||||
e1000_bus_width_pcie_x2,
|
||||
e1000_bus_width_pcie_x4 = 4,
|
||||
e1000_bus_width_pcie_x8 = 8,
|
||||
e1000_bus_width_32,
|
||||
e1000_bus_width_64,
|
||||
e1000_bus_width_reserved
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -95,9 +95,18 @@
|
||||
|
||||
#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
|
||||
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
|
||||
#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
|
||||
/* bit for disabling packet buffer read */
|
||||
#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
|
||||
|
||||
#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
|
||||
|
||||
#define K1_ENTRY_LATENCY 0
|
||||
#define K1_MIN_TIME 1
|
||||
#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */
|
||||
#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */
|
||||
#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
|
||||
|
||||
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
||||
|
||||
#define E1000_ICH_RAR_ENTRIES 7
|
||||
|
@ -70,6 +70,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
|
||||
[board_pchlan] = &e1000_pch_info,
|
||||
[board_pch2lan] = &e1000_pch2_info,
|
||||
[board_pch_lpt] = &e1000_pch_lpt_info,
|
||||
[board_pch_spt] = &e1000_pch_spt_info,
|
||||
};
|
||||
|
||||
struct e1000_reg_info {
|
||||
@ -1796,7 +1797,8 @@ static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
|
||||
}
|
||||
|
||||
/* Reset on uncorrectable ECC error */
|
||||
if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
|
||||
if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt))) {
|
||||
u32 pbeccsts = er32(PBECCSTS);
|
||||
|
||||
adapter->corr_errors +=
|
||||
@ -1876,7 +1878,8 @@ static irqreturn_t e1000_intr(int __always_unused irq, void *data)
|
||||
}
|
||||
|
||||
/* Reset on uncorrectable ECC error */
|
||||
if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
|
||||
if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt))) {
|
||||
u32 pbeccsts = er32(PBECCSTS);
|
||||
|
||||
adapter->corr_errors +=
|
||||
@ -2257,7 +2260,8 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)
|
||||
if (adapter->msix_entries) {
|
||||
ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
|
||||
ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
|
||||
} else if (hw->mac.type == e1000_pch_lpt) {
|
||||
} else if ((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt)) {
|
||||
ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
|
||||
} else {
|
||||
ew32(IMS, IMS_ENABLE_MASK);
|
||||
@ -3014,6 +3018,19 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
|
||||
ew32(TCTL, tctl);
|
||||
|
||||
hw->mac.ops.config_collision_dist(hw);
|
||||
|
||||
/* SPT Si errata workaround to avoid data corruption */
|
||||
if (hw->mac.type == e1000_pch_spt) {
|
||||
u32 reg_val;
|
||||
|
||||
reg_val = er32(IOSFPC);
|
||||
reg_val |= E1000_RCTL_RDMTS_HEX;
|
||||
ew32(IOSFPC, reg_val);
|
||||
|
||||
reg_val = er32(TARC(0));
|
||||
reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
|
||||
ew32(TARC(0), reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -3490,8 +3507,11 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
|
||||
struct e1000_hw *hw = &adapter->hw;
|
||||
u32 incvalue, incperiod, shift;
|
||||
|
||||
/* Make sure clock is enabled on I217 before checking the frequency */
|
||||
if ((hw->mac.type == e1000_pch_lpt) &&
|
||||
/* Make sure clock is enabled on I217/I218/I219 before checking
|
||||
* the frequency
|
||||
*/
|
||||
if (((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt)) &&
|
||||
!(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
|
||||
!(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
|
||||
u32 fextnvm7 = er32(FEXTNVM7);
|
||||
@ -3505,10 +3525,13 @@ s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
|
||||
switch (hw->mac.type) {
|
||||
case e1000_pch2lan:
|
||||
case e1000_pch_lpt:
|
||||
/* On I217, the clock frequency is 25MHz or 96MHz as
|
||||
* indicated by the System Clock Frequency Indication
|
||||
case e1000_pch_spt:
|
||||
/* On I217, I218 and I219, the clock frequency is 25MHz
|
||||
* or 96MHz as indicated by the System Clock Frequency
|
||||
* Indication
|
||||
*/
|
||||
if ((hw->mac.type != e1000_pch_lpt) ||
|
||||
if (((hw->mac.type != e1000_pch_lpt) &&
|
||||
(hw->mac.type != e1000_pch_spt)) ||
|
||||
(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
|
||||
/* Stable 96MHz frequency */
|
||||
incperiod = INCPERIOD_96MHz;
|
||||
@ -3875,6 +3898,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
|
||||
break;
|
||||
case e1000_pch2lan:
|
||||
case e1000_pch_lpt:
|
||||
case e1000_pch_spt:
|
||||
fc->refresh_time = 0x0400;
|
||||
|
||||
if (adapter->netdev->mtu <= ETH_DATA_LEN) {
|
||||
@ -4759,7 +4783,8 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
|
||||
adapter->stats.mgpdc += er32(MGTPDC);
|
||||
|
||||
/* Correctable ECC Errors */
|
||||
if (hw->mac.type == e1000_pch_lpt) {
|
||||
if ((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt)) {
|
||||
u32 pbeccsts = er32(PBECCSTS);
|
||||
|
||||
adapter->corr_errors +=
|
||||
@ -6144,7 +6169,8 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
|
||||
|
||||
if (adapter->hw.phy.type == e1000_phy_igp_3) {
|
||||
e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
|
||||
} else if (hw->mac.type == e1000_pch_lpt) {
|
||||
} else if ((hw->mac.type == e1000_pch_lpt) ||
|
||||
(hw->mac.type == e1000_pch_spt)) {
|
||||
if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
|
||||
/* ULP does not support wake from unicast, multicast
|
||||
* or broadcast.
|
||||
@ -7213,6 +7239,10 @@ static const struct pci_device_id e1000_pci_tbl[] = {
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
|
||||
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
|
||||
};
|
||||
|
@ -221,7 +221,9 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)
|
||||
switch (hw->mac.type) {
|
||||
case e1000_pch2lan:
|
||||
case e1000_pch_lpt:
|
||||
if ((hw->mac.type != e1000_pch_lpt) ||
|
||||
case e1000_pch_spt:
|
||||
if (((hw->mac.type != e1000_pch_lpt) &&
|
||||
(hw->mac.type != e1000_pch_spt)) ||
|
||||
(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
|
||||
adapter->ptp_clock_info.max_adj = 24000000 - 1;
|
||||
break;
|
||||
|
@ -38,6 +38,7 @@
|
||||
#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
|
||||
#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
|
||||
#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
|
||||
#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
|
||||
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
||||
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
|
||||
@ -67,6 +68,7 @@
|
||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
||||
#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
|
||||
#define E1000_IOSFPC 0x00F28 /* TX corrupted data */
|
||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
|
||||
#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
|
||||
@ -121,6 +123,7 @@
|
||||
(0x054E4 + ((_i - 16) * 8)))
|
||||
#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
|
||||
#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
|
||||
#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
|
||||
#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
|
||||
#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
|
||||
#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
|
||||
|
Loading…
Reference in New Issue
Block a user