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clk: meson8b: convert to platform_driver
This patch creates a proper platform_driver for the meson8b clock controller. Use of CLK_OF_DECLARE is removed, and can be added back in later if very early registration of some clocks is required. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -2,6 +2,9 @@
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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@ -17,11 +20,10 @@
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include "clkc.h"
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@ -350,18 +352,19 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
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&meson8b_sys_pll,
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};
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static void __init meson8b_clkc_init(struct device_node *np)
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static int meson8b_clkc_probe(struct platform_device *pdev)
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{
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void __iomem *clk_base;
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int ret, clkid, i;
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struct clk_hw *parent_hw;
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struct clk *parent_clk;
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struct device *dev = &pdev->dev;
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/* Generic clocks and PLLs */
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clk_base = of_iomap(np, 1);
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clk_base = of_iomap(dev->of_node, 1);
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if (!clk_base) {
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pr_err("%s: Unable to map clk base\n", __func__);
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return;
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return -ENXIO;
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}
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/* Populate base address for PLLs */
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@ -386,9 +389,9 @@ static void __init meson8b_clkc_init(struct device_node *np)
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continue;
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/* FIXME convert to devm_clk_register */
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ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[clkid]);
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ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
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if (ret)
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goto unregister;
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goto iounmap;
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}
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/*
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@ -411,17 +414,45 @@ static void __init meson8b_clkc_init(struct device_node *np)
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if (ret) {
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pr_err("%s: failed to register clock notifier for cpu_clk\n",
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__func__);
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goto unregister_clk_nb;
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goto iounmap;
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}
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &meson8b_hw_onecell_data);
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return;
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return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
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&meson8b_hw_onecell_data);
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/* FIXME remove after converting to platform_driver/devm_clk_register */
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unregister_clk_nb:
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clk_notifier_unregister(parent_clk, &meson8b_a5_clk.clk_nb);
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unregister:
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for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
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clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
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iounmap:
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iounmap(clk_base);
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return ret;
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}
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CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);
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static const struct of_device_id meson8b_clkc_match_table[] = {
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{ .compatible = "amlogic,meson8b-clkc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, meson8b_match_table);
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static struct platform_driver meson8b_driver = {
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.probe = meson8b_clkc_probe,
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.driver = {
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.name = "meson8b-clkc",
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.of_match_table = meson8b_clkc_match_table,
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},
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};
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static int __init meson8b_clkc_init(void)
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{
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return platform_driver_register(&meson8b_driver);
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}
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module_init(meson8b_clkc_init);
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static void __exit meson8b_clkc_exit(void)
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{
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platform_driver_unregister(&meson8b_driver);
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}
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module_exit(meson8b_clkc_exit);
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MODULE_DESCRIPTION("AmLogic S805 / Meson8b Clock Controller Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:meson8b-clkc");
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MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
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MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
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