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clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported with separate mux and divider clks. It also adds support for the pre-divider on the PLL6 input, thus allowing the clock to be muxed to PLL6 with proper clock rate calculation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -26,7 +26,7 @@ Required properties:
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
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"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
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@ -20,11 +20,219 @@
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include <linux/log2.h>
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#include "clk-factors.h"
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static DEFINE_SPINLOCK(clk_lock);
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/**
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* sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
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*/
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#define SUN6I_AHB1_MAX_PARENTS 4
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#define SUN6I_AHB1_MUX_PARENT_PLL6 3
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#define SUN6I_AHB1_MUX_SHIFT 12
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/* un-shifted mask is what mux_clk expects */
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#define SUN6I_AHB1_MUX_MASK 0x3
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#define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
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SUN6I_AHB1_MUX_MASK)
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#define SUN6I_AHB1_DIV_SHIFT 4
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#define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
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#define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
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SUN6I_AHB1_DIV_SHIFT)
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#define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
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(div << SUN6I_AHB1_DIV_SHIFT))
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#define SUN6I_AHB1_PLL6_DIV_SHIFT 6
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#define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
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#define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
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SUN6I_AHB1_PLL6_DIV_SHIFT)
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#define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
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(div << SUN6I_AHB1_PLL6_DIV_SHIFT))
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struct sun6i_ahb1_clk {
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struct clk_hw hw;
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void __iomem *reg;
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};
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#define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
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static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
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unsigned long rate;
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u32 reg;
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/* Fetch the register value */
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reg = readl(ahb1->reg);
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/* apply pre-divider first if parent is pll6 */
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if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
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parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
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/* clk divider */
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rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
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return rate;
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}
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static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
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u8 parent, unsigned long parent_rate)
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{
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u8 div, calcp, calcm = 1;
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/*
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* clock can only divide, so we will never be able to achieve
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* frequencies higher than the parent frequency
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*/
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if (parent_rate && rate > parent_rate)
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rate = parent_rate;
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div = DIV_ROUND_UP(parent_rate, rate);
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/* calculate pre-divider if parent is pll6 */
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if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
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if (div < 4)
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calcp = 0;
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else if (div / 2 < 4)
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calcp = 1;
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else if (div / 4 < 4)
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calcp = 2;
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else
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calcp = 3;
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calcm = DIV_ROUND_UP(div, 1 << calcp);
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} else {
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calcp = __roundup_pow_of_two(div);
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calcp = calcp > 3 ? 3 : calcp;
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}
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/* we were asked to pass back divider values */
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if (divp) {
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*divp = calcp;
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*pre_divp = calcm - 1;
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}
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return (parent_rate / calcm) >> calcp;
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}
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static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk)
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{
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struct clk *clk = hw->clk, *parent, *best_parent = NULL;
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int i, num_parents;
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unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
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/* find the parent that can help provide the fastest rate <= rate */
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num_parents = __clk_get_num_parents(clk);
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for (i = 0; i < num_parents; i++) {
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parent = clk_get_parent_by_index(clk, i);
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if (!parent)
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continue;
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if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
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parent_rate = __clk_round_rate(parent, rate);
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else
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parent_rate = __clk_get_rate(parent);
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child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
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parent_rate);
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if (child_rate <= rate && child_rate > best_child_rate) {
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best_parent = parent;
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best = parent_rate;
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best_child_rate = child_rate;
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}
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}
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if (best_parent)
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*best_parent_clk = __clk_get_hw(best_parent);
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*best_parent_rate = best;
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return best_child_rate;
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}
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static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
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unsigned long flags;
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u8 div, pre_div, parent;
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u32 reg;
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spin_lock_irqsave(&clk_lock, flags);
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reg = readl(ahb1->reg);
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/* need to know which parent is used to apply pre-divider */
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parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
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sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
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reg = SUN6I_AHB1_DIV_SET(reg, div);
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reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
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writel(reg, ahb1->reg);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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static const struct clk_ops sun6i_ahb1_clk_ops = {
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.determine_rate = sun6i_ahb1_clk_determine_rate,
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.recalc_rate = sun6i_ahb1_clk_recalc_rate,
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.set_rate = sun6i_ahb1_clk_set_rate,
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};
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static void __init sun6i_ahb1_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct sun6i_ahb1_clk *ahb1;
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struct clk_mux *mux;
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const char *clk_name = node->name;
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const char *parents[SUN6I_AHB1_MAX_PARENTS];
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void __iomem *reg;
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int i = 0;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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/* we have a mux, we will have >1 parents */
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while (i < SUN6I_AHB1_MAX_PARENTS &&
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(parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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i++;
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of_property_read_string(node, "clock-output-names", &clk_name);
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ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
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if (!ahb1)
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return;
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux) {
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kfree(ahb1);
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return;
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}
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/* set up clock properties */
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mux->reg = reg;
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mux->shift = SUN6I_AHB1_MUX_SHIFT;
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mux->mask = SUN6I_AHB1_MUX_MASK;
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mux->lock = &clk_lock;
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ahb1->reg = reg;
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clk = clk_register_composite(NULL, clk_name, parents, i,
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&mux->hw, &clk_mux_ops,
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&ahb1->hw, &sun6i_ahb1_clk_ops,
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NULL, NULL, 0);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
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/* Maximum number of parents our clocks have */
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#define SUNXI_MAX_PARENTS 5
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