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drm/mediatek: adjust EDGE to match clock and data
The default timing of DPI data and clock is not match. We could adjust this bit to make them match. Signed-off-by: chunhui dai <chunhui.dai@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
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@ -114,6 +114,7 @@ struct mtk_dpi_yc_limit {
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struct mtk_dpi_conf {
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u32 reg_h_fre_con;
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bool edge_sel_en;
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};
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static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
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@ -344,6 +345,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
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}
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static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
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{
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if (dpi->conf->edge_sel_en)
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
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}
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static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
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enum mtk_dpi_out_color_format format)
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{
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@ -507,6 +514,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
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mtk_dpi_config_yc_map(dpi, dpi->yc_map);
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mtk_dpi_config_color_format(dpi, dpi->color_format);
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mtk_dpi_config_2n_h_fre(dpi);
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mtk_dpi_config_disable_edge(dpi);
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mtk_dpi_sw_reset(dpi, false);
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return 0;
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@ -223,5 +223,6 @@
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#define ESAV_CODE2 (0xFFF << 0)
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#define ESAV_CODE3_MSB BIT(16)
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#define EDGE_SEL_EN BIT(5)
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#define H_FRE_2N BIT(25)
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#endif /* __MTK_DPI_REGS_H */
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