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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mtd: spi-nor: Describe all the Reg Ops
Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Tudor Ambarus
parent
6e3087a863
commit
78f1ddf7bb
@ -388,9 +388,11 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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return nor->controller_ops->write(nor, to, len, buf);
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}
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/*
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* Set write enable latch with Write Enable command.
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* Returns negative if error occurred.
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/**
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* spi_nor_write_enable() - Set write enable latch with Write Enable command.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_enable(struct spi_nor *nor)
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{
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@ -415,8 +417,11 @@ static int spi_nor_write_enable(struct spi_nor *nor)
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return ret;
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}
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/*
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* Send write disable instruction to the chip.
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/**
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* spi_nor_write_disable() - Send Write Disable instruction to the chip.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_disable(struct spi_nor *nor)
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{
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@ -534,6 +539,14 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
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return ret;
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}
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/**
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* macronix_set_4byte() - Set 4-byte address mode for Macronix flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int macronix_set_4byte(struct spi_nor *nor, bool enable)
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{
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int ret;
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@ -562,6 +575,14 @@ static int macronix_set_4byte(struct spi_nor *nor, bool enable)
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return ret;
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}
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/**
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* st_micron_set_4byte() - Set 4-byte address mode for ST and Micron flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
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{
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int ret;
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@ -577,6 +598,14 @@ static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
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return spi_nor_write_disable(nor);
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}
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/**
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* spansion_set_4byte() - Set 4-byte address mode for Spansion flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spansion_set_4byte(struct spi_nor *nor, bool enable)
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{
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int ret;
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@ -602,6 +631,13 @@ static int spansion_set_4byte(struct spi_nor *nor, bool enable)
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return ret;
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}
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/**
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* spi_nor_write_ear() - Write Extended Address Register.
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* @nor: pointer to 'struct spi_nor'.
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* @ear: value to write to the Extended Address Register.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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{
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int ret;
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@ -627,6 +663,14 @@ static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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return ret;
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}
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/**
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* winbond_set_4byte() - Set 4-byte address mode for Winbond flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
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* address mode.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int winbond_set_4byte(struct spi_nor *nor, bool enable)
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{
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int ret;
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@ -651,6 +695,14 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
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return spi_nor_write_disable(nor);
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}
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/**
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* spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @sr: pointer to a DMA-able buffer where the value of the
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* Status Register will be written.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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{
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int ret;
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@ -674,6 +726,13 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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return ret;
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}
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/**
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* s3an_sr_ready() - Query the Status Register of the S3AN flash to see if the
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* flash is ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int s3an_sr_ready(struct spi_nor *nor)
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{
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int ret;
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@ -685,6 +744,10 @@ static int s3an_sr_ready(struct spi_nor *nor)
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return !!(nor->bouncebuf[0] & XSR_RDY);
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}
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/**
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* spi_nor_clear_sr() - Clear the Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_sr(struct spi_nor *nor)
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{
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int ret;
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@ -706,6 +769,13 @@ static void spi_nor_clear_sr(struct spi_nor *nor)
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dev_dbg(nor->dev, "error %d clearing SR\n", ret);
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}
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/**
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* spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
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* for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_sr_ready(struct spi_nor *nor)
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{
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int ret = spi_nor_read_sr(nor, nor->bouncebuf);
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@ -727,6 +797,10 @@ static int spi_nor_sr_ready(struct spi_nor *nor)
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return !(nor->bouncebuf[0] & SR_WIP);
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}
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/**
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* spi_nor_clear_fsr() - Clear the Flag Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_fsr(struct spi_nor *nor)
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{
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int ret;
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@ -748,6 +822,13 @@ static void spi_nor_clear_fsr(struct spi_nor *nor)
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dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
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}
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/**
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* spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
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* ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_fsr_ready(struct spi_nor *nor)
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{
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int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
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@ -772,6 +853,12 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
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return nor->bouncebuf[0] & FSR_READY;
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}
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/**
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* spi_nor_ready() - Query the flash to see if it is ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_ready(struct spi_nor *nor)
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{
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int sr, fsr;
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@ -788,9 +875,13 @@ static int spi_nor_ready(struct spi_nor *nor)
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return sr && fsr;
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}
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/*
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* Service routine to read status register until ready, or timeout occurs.
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* Returns non-zero if error.
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/**
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* spi_nor_wait_till_ready_with_timeout() - Service routine to read the
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* Status Register until ready, or timeout occurs.
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* @nor: pointer to "struct spi_nor".
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* @timeout_jiffies: jiffies to wait until timeout.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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unsigned long timeout_jiffies)
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@ -818,6 +909,13 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
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return -ETIMEDOUT;
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}
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/**
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* spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
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* flash to be ready, or timeout occurs.
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* @nor: pointer to "struct spi_nor".
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_wait_till_ready(struct spi_nor *nor)
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{
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return spi_nor_wait_till_ready_with_timeout(nor,
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@ -880,6 +978,14 @@ static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new,
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return ((nor->bouncebuf[0] & mask) != (status_new & mask)) ? -EIO : 0;
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}
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/**
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* spi_nor_write_sr2() - Write the Status Register 2 using the
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* SPINOR_OP_WRSR2 (3eh) command.
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* @nor: pointer to 'struct spi_nor'.
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* @sr2: pointer to DMA-able buffer to write to the Status Register 2.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
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{
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int ret;
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@ -909,6 +1015,15 @@ static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
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return spi_nor_wait_till_ready(nor);
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}
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/**
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* spi_nor_read_sr2() - Read the Status Register 2 using the
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* SPINOR_OP_RDSR2 (3fh) command.
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* @nor: pointer to 'struct spi_nor'.
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* @sr2: pointer to DMA-able buffer where the value of the
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* Status Register 2 will be written.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
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{
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int ret;
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@ -932,10 +1047,11 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
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return ret;
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}
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/*
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* Erase the whole flash memory
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/**
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* spi_nor_erase_chip() - Erase the entire flash memory.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Returns 0 if successful, non-zero otherwise.
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_erase_chip(struct spi_nor *nor)
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{
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