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ARM: mx5: Add watchdog support for MX53
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -1336,6 +1336,8 @@ static struct clk_lookup mx53_lookups[] = {
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_REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
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_REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
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_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
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_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
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_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
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};
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static void clk_tree_init(void)
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@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
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extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
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#define imx53_add_ecspi(id, pdata) \
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imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
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extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
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#define imx53_add_imx2_wdt(id, pdata) \
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imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
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@ -66,7 +66,7 @@ void __init imx53_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX53);
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mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
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mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
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}
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int imx51_register_gpios(void);
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@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
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};
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#endif /* ifdef CONFIG_SOC_IMX51 */
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#ifdef CONFIG_SOC_IMX53
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const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
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#define imx53_imx2_wdt_data_entry(_id, _hwid) \
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imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
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imx53_imx2_wdt_data_entry(0, 1),
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imx53_imx2_wdt_data_entry(1, 2),
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};
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#endif /* ifdef CONFIG_SOC_IMX53 */
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struct platform_device *__init imx_add_imx2_wdt(
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const struct imx_imx2_wdt_data *data)
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{
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@ -79,7 +79,7 @@
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#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
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#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
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#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
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#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
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#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
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#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
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#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
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#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
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