mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 03:26:41 +07:00
drm/amdkfd: Add wave control operation to debugger
The wave control operation supports several command types executed upon existing wave fronts that belong to the currently debugged process. The available commands are: HALT - Freeze wave front(s) execution RESUME - Resume freezed wave front(s) execution KILL - Kill existing wave front(s) Signed-off-by: Yair Shachar <yair.shachar@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
This commit is contained in:
Yair Shachar
Oded Gabbay
parent
fbeb661bfa
commit
788bf83db3
@ -47,6 +47,125 @@ static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)
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dev->kfd2kgd->address_watch_disable(dev->kgd);
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}
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static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
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unsigned int pasid, uint64_t vmid0_address,
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uint32_t *packet_buff, size_t size_in_bytes)
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{
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struct pm4__release_mem *rm_packet;
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struct pm4__indirect_buffer_pasid *ib_packet;
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struct kfd_mem_obj *mem_obj;
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size_t pq_packets_size_in_bytes;
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union ULARGE_INTEGER *largep;
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union ULARGE_INTEGER addr;
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struct kernel_queue *kq;
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uint64_t *rm_state;
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unsigned int *ib_packet_buff;
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int status;
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BUG_ON(!dbgdev || !dbgdev->kq || !packet_buff || !size_in_bytes);
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kq = dbgdev->kq;
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pq_packets_size_in_bytes = sizeof(struct pm4__release_mem) +
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sizeof(struct pm4__indirect_buffer_pasid);
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/*
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* We acquire a buffer from DIQ
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* The receive packet buff will be sitting on the Indirect Buffer
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* and in the PQ we put the IB packet + sync packet(s).
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*/
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status = kq->ops.acquire_packet_buffer(kq,
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pq_packets_size_in_bytes / sizeof(uint32_t),
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&ib_packet_buff);
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if (status != 0) {
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pr_err("amdkfd: acquire_packet_buffer failed\n");
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return status;
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}
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memset(ib_packet_buff, 0, pq_packets_size_in_bytes);
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ib_packet = (struct pm4__indirect_buffer_pasid *) (ib_packet_buff);
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ib_packet->header.count = 3;
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ib_packet->header.opcode = IT_INDIRECT_BUFFER_PASID;
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ib_packet->header.type = PM4_TYPE_3;
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largep = (union ULARGE_INTEGER *) &vmid0_address;
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ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2;
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ib_packet->bitfields3.ib_base_hi = largep->u.high_part;
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ib_packet->control = (1 << 23) | (1 << 31) |
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((size_in_bytes / sizeof(uint32_t)) & 0xfffff);
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ib_packet->bitfields5.pasid = pasid;
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/*
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* for now we use release mem for GPU-CPU synchronization
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* Consider WaitRegMem + WriteData as a better alternative
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* we get a GART allocations ( gpu/cpu mapping),
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* for the sync variable, and wait until:
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* (a) Sync with HW
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* (b) Sync var is written by CP to mem.
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*/
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rm_packet = (struct pm4__release_mem *) (ib_packet_buff +
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(sizeof(struct pm4__indirect_buffer_pasid) /
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sizeof(unsigned int)));
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status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t),
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&mem_obj);
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if (status != 0) {
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pr_err("amdkfd: Failed to allocate GART memory\n");
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kq->ops.rollback_packet(kq);
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return status;
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}
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rm_state = (uint64_t *) mem_obj->cpu_ptr;
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*rm_state = QUEUESTATE__ACTIVE_COMPLETION_PENDING;
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rm_packet->header.opcode = IT_RELEASE_MEM;
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rm_packet->header.type = PM4_TYPE_3;
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rm_packet->header.count = sizeof(struct pm4__release_mem) /
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sizeof(unsigned int) - 2;
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rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
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rm_packet->bitfields2.event_index =
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event_index___release_mem__end_of_pipe;
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rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
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rm_packet->bitfields2.atc = 0;
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rm_packet->bitfields2.tc_wb_action_ena = 1;
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addr.quad_part = mem_obj->gpu_addr;
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rm_packet->bitfields4.address_lo_32b = addr.u.low_part >> 2;
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rm_packet->address_hi = addr.u.high_part;
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rm_packet->bitfields3.data_sel =
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data_sel___release_mem__send_64_bit_data;
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rm_packet->bitfields3.int_sel =
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int_sel___release_mem__send_data_after_write_confirm;
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rm_packet->bitfields3.dst_sel =
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dst_sel___release_mem__memory_controller;
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rm_packet->data_lo = QUEUESTATE__ACTIVE;
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kq->ops.submit_packet(kq);
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/* Wait till CP writes sync code: */
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status = amdkfd_fence_wait_timeout(
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(unsigned int *) rm_state,
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QUEUESTATE__ACTIVE, 1500);
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kfd_gtt_sa_free(dbgdev->dev, mem_obj);
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return status;
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}
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static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev)
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{
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BUG_ON(!dbgdev);
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@ -117,6 +236,290 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev)
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return status;
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}
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static int dbgdev_wave_control_set_registers(
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struct dbg_wave_control_info *wac_info,
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union SQ_CMD_BITS *in_reg_sq_cmd,
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union GRBM_GFX_INDEX_BITS *in_reg_gfx_index)
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{
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int status;
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union SQ_CMD_BITS reg_sq_cmd;
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union GRBM_GFX_INDEX_BITS reg_gfx_index;
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struct HsaDbgWaveMsgAMDGen2 *pMsg;
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BUG_ON(!wac_info || !in_reg_sq_cmd || !in_reg_gfx_index);
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reg_sq_cmd.u32All = 0;
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reg_gfx_index.u32All = 0;
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pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2;
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switch (wac_info->mode) {
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/* Send command to single wave */
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case HSA_DBG_WAVEMODE_SINGLE:
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/*
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* Limit access to the process waves only,
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* by setting vmid check
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*/
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reg_sq_cmd.bits.check_vmid = 1;
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reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD;
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reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId;
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reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE;
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reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
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reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
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reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
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break;
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/* Send command to all waves with matching VMID */
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case HSA_DBG_WAVEMODE_BROADCAST_PROCESS:
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reg_gfx_index.bits.sh_broadcast_writes = 1;
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reg_gfx_index.bits.se_broadcast_writes = 1;
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reg_gfx_index.bits.instance_broadcast_writes = 1;
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reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
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break;
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/* Send command to all CU waves with matching VMID */
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case HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU:
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reg_sq_cmd.bits.check_vmid = 1;
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reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
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reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
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reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
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reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
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break;
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default:
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return -EINVAL;
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}
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switch (wac_info->operand) {
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case HSA_DBG_WAVEOP_HALT:
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reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT;
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break;
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case HSA_DBG_WAVEOP_RESUME:
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reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME;
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break;
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case HSA_DBG_WAVEOP_KILL:
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reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
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break;
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case HSA_DBG_WAVEOP_DEBUG:
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reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG;
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break;
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case HSA_DBG_WAVEOP_TRAP:
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if (wac_info->trapId < MAX_TRAPID) {
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reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP;
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reg_sq_cmd.bits.trap_id = wac_info->trapId;
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} else {
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status = -EINVAL;
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}
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break;
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default:
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status = -EINVAL;
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break;
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}
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if (status == 0) {
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*in_reg_sq_cmd = reg_sq_cmd;
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*in_reg_gfx_index = reg_gfx_index;
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}
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return status;
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}
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static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
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struct dbg_wave_control_info *wac_info)
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{
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int status;
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union SQ_CMD_BITS reg_sq_cmd;
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union GRBM_GFX_INDEX_BITS reg_gfx_index;
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struct kfd_mem_obj *mem_obj;
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uint32_t *packet_buff_uint;
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struct pm4__set_config_reg *packets_vec;
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size_t ib_size = sizeof(struct pm4__set_config_reg) * 3;
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BUG_ON(!dbgdev || !wac_info);
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reg_sq_cmd.u32All = 0;
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status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd,
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®_gfx_index);
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if (status) {
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pr_err("amdkfd: Failed to set wave control registers\n");
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return status;
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}
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/* we do not control the VMID in DIQ,so reset it to a known value */
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reg_sq_cmd.bits.vm_id = 0;
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pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t mode is: %u\n", wac_info->mode);
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pr_debug("\t\t operand is: %u\n", wac_info->operand);
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pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
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pr_debug("\t\t msg value is: %u\n",
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wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
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pr_debug("\t\t vmid is: N/A\n");
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pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
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pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
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pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
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pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
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pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
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pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
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pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
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pr_debug("\t\t ibw is : %u\n",
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reg_gfx_index.bitfields.instance_broadcast_writes);
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pr_debug("\t\t ii is : %u\n",
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reg_gfx_index.bitfields.instance_index);
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pr_debug("\t\t sebw is : %u\n",
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reg_gfx_index.bitfields.se_broadcast_writes);
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pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
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pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
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pr_debug("\t\t sbw is : %u\n",
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reg_gfx_index.bitfields.sh_broadcast_writes);
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pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
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status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
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if (status != 0) {
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pr_err("amdkfd: Failed to allocate GART memory\n");
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return status;
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}
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packet_buff_uint = mem_obj->cpu_ptr;
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memset(packet_buff_uint, 0, ib_size);
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packets_vec = (struct pm4__set_config_reg *) packet_buff_uint;
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packets_vec[0].header.count = 1;
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packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;
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packets_vec[0].header.type = PM4_TYPE_3;
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packets_vec[0].bitfields2.reg_offset =
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GRBM_GFX_INDEX / (sizeof(uint32_t)) -
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USERCONFIG_REG_BASE;
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packets_vec[0].bitfields2.insert_vmid = 0;
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packets_vec[0].reg_data[0] = reg_gfx_index.u32All;
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packets_vec[1].header.count = 1;
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packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
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packets_vec[1].header.type = PM4_TYPE_3;
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packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
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CONFIG_REG_BASE;
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packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
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packets_vec[1].bitfields2.insert_vmid = 1;
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packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;
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/* Restore the GRBM_GFX_INDEX register */
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reg_gfx_index.u32All = 0;
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reg_gfx_index.bits.sh_broadcast_writes = 1;
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reg_gfx_index.bits.instance_broadcast_writes = 1;
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reg_gfx_index.bits.se_broadcast_writes = 1;
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packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
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packets_vec[2].bitfields2.reg_offset =
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GRBM_GFX_INDEX / (sizeof(uint32_t)) -
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USERCONFIG_REG_BASE;
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packets_vec[2].bitfields2.insert_vmid = 0;
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packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
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status = dbgdev_diq_submit_ib(
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dbgdev,
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wac_info->process->pasid,
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mem_obj->gpu_addr,
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packet_buff_uint,
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ib_size);
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if (status != 0)
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pr_err("amdkfd: Failed to submit IB to DIQ\n");
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kfd_gtt_sa_free(dbgdev->dev, mem_obj);
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return status;
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}
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static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev,
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struct dbg_wave_control_info *wac_info)
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{
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int status;
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union SQ_CMD_BITS reg_sq_cmd;
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union GRBM_GFX_INDEX_BITS reg_gfx_index;
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struct kfd_process_device *pdd;
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BUG_ON(!dbgdev || !dbgdev->dev || !wac_info);
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reg_sq_cmd.u32All = 0;
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/* taking the VMID for that process on the safe way using PDD */
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pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process);
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if (!pdd) {
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pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n");
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return -EFAULT;
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}
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status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd,
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®_gfx_index);
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if (status) {
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pr_err("amdkfd: Failed to set wave control registers\n");
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return status;
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}
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/* for non DIQ we need to patch the VMID: */
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reg_sq_cmd.bits.vm_id = pdd->qpd.vmid;
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pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
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pr_debug("\t\t mode is: %u\n", wac_info->mode);
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pr_debug("\t\t operand is: %u\n", wac_info->operand);
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pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
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pr_debug("\t\t msg value is: %u\n",
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wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
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pr_debug("\t\t vmid is: %u\n", pdd->qpd.vmid);
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pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
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pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
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pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
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pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
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pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
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pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
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pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
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pr_debug("\t\t ibw is : %u\n",
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reg_gfx_index.bitfields.instance_broadcast_writes);
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pr_debug("\t\t ii is : %u\n",
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reg_gfx_index.bitfields.instance_index);
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pr_debug("\t\t sebw is : %u\n",
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reg_gfx_index.bitfields.se_broadcast_writes);
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||||
pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
|
||||
pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
|
||||
pr_debug("\t\t sbw is : %u\n",
|
||||
reg_gfx_index.bitfields.sh_broadcast_writes);
|
||||
|
||||
pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
|
||||
|
||||
return dbgdev->dev->kfd2kgd->wave_control_execute(dbgdev->dev->kgd,
|
||||
reg_gfx_index.u32All,
|
||||
reg_sq_cmd.u32All);
|
||||
}
|
||||
|
||||
void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
|
||||
enum DBGDEV_TYPE type)
|
||||
{
|
||||
@ -131,11 +534,13 @@ void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
|
||||
case DBGDEV_TYPE_NODIQ:
|
||||
pdbgdev->dbgdev_register = dbgdev_register_nodiq;
|
||||
pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq;
|
||||
pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq;
|
||||
break;
|
||||
case DBGDEV_TYPE_DIQ:
|
||||
default:
|
||||
pdbgdev->dbgdev_register = dbgdev_register_diq;
|
||||
pdbgdev->dbgdev_unregister = dbgdev_unregister_diq;
|
||||
pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -133,3 +133,19 @@ long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
|
||||
struct dbg_wave_control_info *wac_info)
|
||||
{
|
||||
BUG_ON(!pmgr || !pmgr->dbgdev || !wac_info);
|
||||
|
||||
/* Is the requests coming from the already registered process? */
|
||||
if (pmgr->pasid != wac_info->process->pasid) {
|
||||
pr_debug("H/W debugger support was not registered for requester pasid %d\n",
|
||||
wac_info->process->pasid);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info);
|
||||
}
|
||||
|
||||
|
||||
@ -268,6 +268,8 @@ struct kfd_dbgdev {
|
||||
/* virtualized function pointers to device dbg */
|
||||
int (*dbgdev_register)(struct kfd_dbgdev *dbgdev);
|
||||
int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev);
|
||||
int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev,
|
||||
struct dbg_wave_control_info *wac_info);
|
||||
|
||||
};
|
||||
|
||||
@ -283,5 +285,6 @@ void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr);
|
||||
bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev);
|
||||
long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
|
||||
long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
|
||||
|
||||
long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
|
||||
struct dbg_wave_control_info *wac_info);
|
||||
#endif /* KFD_DBGMGR_H_ */
|
||||
|
||||
@ -915,7 +915,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
|
||||
int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
|
||||
unsigned int fence_value,
|
||||
unsigned long timeout)
|
||||
{
|
||||
|
||||
@ -656,6 +656,10 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid,
|
||||
struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,
|
||||
unsigned int qid);
|
||||
|
||||
int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
|
||||
unsigned int fence_value,
|
||||
unsigned long timeout);
|
||||
|
||||
/* Packet Manager */
|
||||
|
||||
#define KFD_HIQ_TIMEOUT (500)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user