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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
mlx5: convert to generic pci_alloc_irq_vectors
Now that we have a generic code to allocate an array of irq vectors and even correctly spread their affinity, correctly handle cpu hotplug events and more, were much better off using it. Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Doug Ledford <dledford@redhat.com>
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520eccdfe1
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78249c4215
@ -397,7 +397,7 @@ static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
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static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
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{
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clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
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synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
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synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
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}
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static inline int mlx5e_get_wqe_mtt_sz(void)
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@ -585,7 +585,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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name, pci_name(dev->pdev));
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eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
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eq->irqn = priv->msix_arr[vecidx].vector;
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eq->irqn = pci_irq_vector(dev->pdev, vecidx);
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eq->dev = dev;
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eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
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err = request_irq(eq->irqn, handler, 0,
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@ -620,7 +620,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
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return 0;
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err_irq:
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free_irq(priv->msix_arr[vecidx].vector, eq);
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free_irq(eq->irqn, eq);
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err_eq:
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mlx5_cmd_destroy_eq(dev, eq->eqn);
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@ -661,11 +661,6 @@ int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
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}
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EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
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u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
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{
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return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
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}
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int mlx5_eq_init(struct mlx5_core_dev *dev)
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{
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int err;
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@ -1585,7 +1585,7 @@ static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
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/* Mark this vport as disabled to discard new events */
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vport->enabled = false;
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synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
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synchronize_irq(pci_irq_vector(esw->dev->pdev, MLX5_EQ_VEC_ASYNC));
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/* Wait for current already scheduled events to complete */
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flush_workqueue(esw->work_queue);
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/* Disable events from this vport */
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@ -81,7 +81,7 @@ static void trigger_cmd_completions(struct mlx5_core_dev *dev)
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u64 vector;
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/* wait for pending handlers to complete */
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synchronize_irq(dev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector);
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synchronize_irq(pci_irq_vector(dev->pdev, MLX5_EQ_VEC_CMD));
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spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
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vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
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if (!vector)
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@ -312,13 +312,12 @@ static void release_bar(struct pci_dev *pdev)
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pci_release_regions(pdev);
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}
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static int mlx5_enable_msix(struct mlx5_core_dev *dev)
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static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
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{
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struct mlx5_priv *priv = &dev->priv;
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struct mlx5_eq_table *table = &priv->eq_table;
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int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
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int nvec;
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int i;
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nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
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MLX5_EQ_VEC_COMP_BASE;
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@ -326,17 +325,13 @@ static int mlx5_enable_msix(struct mlx5_core_dev *dev)
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if (nvec <= MLX5_EQ_VEC_COMP_BASE)
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return -ENOMEM;
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priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
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priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
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if (!priv->msix_arr || !priv->irq_info)
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if (!priv->irq_info)
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goto err_free_msix;
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for (i = 0; i < nvec; i++)
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priv->msix_arr[i].entry = i;
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nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
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MLX5_EQ_VEC_COMP_BASE + 1, nvec);
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nvec = pci_alloc_irq_vectors(dev->pdev,
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MLX5_EQ_VEC_COMP_BASE + 1, nvec,
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PCI_IRQ_MSIX);
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if (nvec < 0)
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return nvec;
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@ -346,17 +341,15 @@ static int mlx5_enable_msix(struct mlx5_core_dev *dev)
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err_free_msix:
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kfree(priv->irq_info);
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kfree(priv->msix_arr);
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return -ENOMEM;
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}
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static void mlx5_disable_msix(struct mlx5_core_dev *dev)
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static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
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{
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struct mlx5_priv *priv = &dev->priv;
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pci_disable_msix(dev->pdev);
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pci_free_irq_vectors(dev->pdev);
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kfree(priv->irq_info);
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kfree(priv->msix_arr);
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}
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struct mlx5_reg_host_endianness {
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@ -615,8 +608,7 @@ u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
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static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
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{
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struct mlx5_priv *priv = &mdev->priv;
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struct msix_entry *msix = priv->msix_arr;
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int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
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int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
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if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
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mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
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@ -636,8 +628,7 @@ static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
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static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
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{
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struct mlx5_priv *priv = &mdev->priv;
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struct msix_entry *msix = priv->msix_arr;
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int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
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int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
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irq_set_affinity_hint(irq, NULL);
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free_cpumask_var(priv->irq_info[i].mask);
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@ -760,8 +751,8 @@ static int alloc_comp_eqs(struct mlx5_core_dev *dev)
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}
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#ifdef CONFIG_RFS_ACCEL
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irq_cpu_rmap_add(dev->rmap,
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dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
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irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
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MLX5_EQ_VEC_COMP_BASE + i));
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#endif
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
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err = mlx5_create_map_eq(dev, eq,
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@ -1119,9 +1110,9 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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goto err_stop_poll;
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}
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err = mlx5_enable_msix(dev);
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err = mlx5_alloc_irq_vectors(dev);
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if (err) {
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dev_err(&pdev->dev, "enable msix failed\n");
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dev_err(&pdev->dev, "alloc irq vectors failed\n");
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goto err_cleanup_once;
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}
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@ -1220,7 +1211,7 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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mlx5_put_uars_page(dev, priv->uar);
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err_disable_msix:
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mlx5_disable_msix(dev);
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mlx5_free_irq_vectors(dev);
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err_cleanup_once:
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if (boot)
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@ -1287,7 +1278,7 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
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free_comp_eqs(dev);
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mlx5_stop_eqs(dev);
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mlx5_put_uars_page(dev, priv->uar);
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mlx5_disable_msix(dev);
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mlx5_free_irq_vectors(dev);
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if (cleanup)
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mlx5_cleanup_once(dev);
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mlx5_stop_health_poll(dev);
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@ -110,7 +110,6 @@ int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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u32 element_id);
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int mlx5_wait_for_vf_pages(struct mlx5_core_dev *dev);
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u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev);
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u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx);
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struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn);
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void mlx5_cq_tasklet_cb(unsigned long data);
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@ -597,7 +597,6 @@ struct mlx5_port_module_event_stats {
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struct mlx5_priv {
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char name[MLX5_MAX_NAME_LEN];
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struct mlx5_eq_table eq_table;
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struct msix_entry *msix_arr;
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struct mlx5_irq_info *irq_info;
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/* pages stuff */
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