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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim <kgene.kim@samsung.com>: This is general development for Samsung stuff for v3.6 * 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API ARM: EXYNOS: Add missing static storage class specifier in pmu.c file ARM: EXYNOS: Make combiner_init function static ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12 ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
77e77e1b61
@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
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.map = combiner_irq_domain_map,
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};
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void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
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static void __init combiner_init(void __iomem *combiner_base,
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struct device_node *np)
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{
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int i, irq, irq_base;
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unsigned int max_nr, nr_irq;
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@ -232,6 +232,11 @@
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#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
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#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
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#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
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#define EXYNOS5_SYS_WDTRESET (1 << 20)
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#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
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@ -35,11 +35,21 @@
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#define PHY1_COMMON_ON_N (1 << 7)
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#define PHY0_COMMON_ON_N (1 << 4)
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#define PHY0_ID_PULLUP (1 << 2)
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#define CLKSEL_MASK (0x3 << 0)
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#define CLKSEL_SHIFT (0)
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#define CLKSEL_48M (0x0 << 0)
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#define CLKSEL_12M (0x2 << 0)
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#define CLKSEL_24M (0x3 << 0)
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#define EXYNOS4_CLKSEL_SHIFT (0)
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#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
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#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
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#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
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#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
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#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
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#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
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#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
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#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
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#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
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#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
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#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
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#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
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#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
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@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
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{ PMU_TABLE_END,},
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};
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void __iomem *exynos5_list_both_cnt_feed[] = {
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static void __iomem *exynos5_list_both_cnt_feed[] = {
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EXYNOS5_ARM_CORE0_OPTION,
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EXYNOS5_ARM_CORE1_OPTION,
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EXYNOS5_ARM_COMMON_OPTION,
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@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
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EXYNOS5_TOP_PWR_SYSMEM_OPTION,
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};
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void __iomem *exynos5_list_diable_wfi_wfe[] = {
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static void __iomem *exynos5_list_diable_wfi_wfe[] = {
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EXYNOS5_ARM_CORE1_OPTION,
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EXYNOS5_FSYS_ARM_OPTION,
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EXYNOS5_ISP_ARM_OPTION,
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@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
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static int __init exynos_pmu_init(void)
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{
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unsigned int value;
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exynos_pmu_config = exynos4210_pmu_config;
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if (soc_is_exynos4210()) {
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@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
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exynos_pmu_config = exynos4x12_pmu_config;
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pr_info("EXYNOS4x12 PMU Initialize\n");
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} else if (soc_is_exynos5250()) {
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/*
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* When SYS_WDTRESET is set, watchdog timer reset request
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* is ignored by power management unit.
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*/
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value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
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value &= ~EXYNOS5_SYS_WDTRESET;
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__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
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value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
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value &= ~EXYNOS5_SYS_WDTRESET;
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__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
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exynos_pmu_config = exynos5250_pmu_config;
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pr_info("EXYNOS5250 PMU Initialize\n");
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} else {
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@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
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struct clk *xusbxti_clk;
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u32 phyclk;
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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if (soc_is_exynos4210()) {
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_12M;
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break;
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case 48 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_48M;
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break;
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default:
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case 24 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_24M;
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break;
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
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switch (clk_get_rate(xusbxti_clk)) {
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case 9600 * KHZ:
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phyclk |= EXYNOS4X12_CLKSEL_9600K;
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break;
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case 10 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_10M;
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break;
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case 12 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_12M;
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break;
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case 19200 * KHZ:
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phyclk |= EXYNOS4X12_CLKSEL_19200K;
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break;
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case 20 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_20M;
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break;
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default:
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case 24 * MHZ:
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/* default reference clock */
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phyclk |= EXYNOS4X12_CLKSEL_24M;
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break;
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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}
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static int exynos4210_usb_phy0_init(struct platform_device *pdev)
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@ -78,6 +78,10 @@ config S5P_HRT
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# clock options
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config SAMSUNG_CLOCK
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bool
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default y if !COMMON_CLK
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config SAMSUNG_CLKSRC
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bool
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help
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@ -15,8 +15,8 @@ obj-y += init.o cpu.o
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obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
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obj-$(CONFIG_S5P_HRT) += s5p-time.o
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obj-y += clock.o
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obj-y += pwm-clock.o
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obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
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obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o
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obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
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obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
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@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
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#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
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#ifndef KHZ
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#define KHZ (1000)
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#endif
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#ifndef MHZ
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#define MHZ (1000*1000)
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#endif
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