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[media] s5p-mfc: Prepare driver for callback based re-architecture

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The patch renames hardware specific opr and cmd files to
opr_v5 and cmd_v5 respectively. This is done for accomodating
firmware v6. Also the shared memory management files are removed
and the functionality is added to the opr_v5 file.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Acked-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Arun Kumar K 2012-10-03 22:19:07 -03:00 committed by Mauro Carvalho Chehab
parent 2e81dde943
commit 77a788fc2d
11 changed files with 151 additions and 189 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/media/platform/s5p-mfc/Makefile
View File

@ -1,5 +1,5 @@
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) := s5p-mfc.o
s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o s5p_mfc_opr.o
s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o s5p_mfc_opr_v5.o
s5p-mfc-y += s5p_mfc_dec.o s5p_mfc_enc.o
s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_cmd.o
s5p-mfc-y += s5p_mfc_pm.o s5p_mfc_shm.o
s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_cmd_v5.o
s5p-mfc-y += s5p_mfc_pm.o

11
drivers/media/platform/s5p-mfc/s5p_mfc.c
View File

@ -28,9 +28,8 @@
#include "s5p_mfc_dec.h"
#include "s5p_mfc_enc.h"
#include "s5p_mfc_intr.h"
#include "s5p_mfc_opr.h"
#include "s5p_mfc_opr_v5.h"
#include "s5p_mfc_pm.h"
#include "s5p_mfc_shm.h"
#define S5P_MFC_NAME "s5p-mfc"
#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
@ -213,8 +212,8 @@ static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
ctx->dst_queue_cnt--;
dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
if (s5p_mfc_read_shm(ctx, PIC_TIME_TOP) ==
s5p_mfc_read_shm(ctx, PIC_TIME_BOT))
if (s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP) ==
s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT))
dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
else
dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
@ -285,8 +284,8 @@ static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
list_del(&dst_buf->list);
ctx->dst_queue_cnt--;
dst_buf->b->v4l2_buf.sequence = ctx->sequence;
if (s5p_mfc_read_shm(ctx, PIC_TIME_TOP) ==
s5p_mfc_read_shm(ctx, PIC_TIME_BOT))
if (s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP) ==
s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT))
dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
else
dst_buf->b->v4l2_buf.field =

2
drivers/media/platform/s5p-mfc/s5p_mfc_cmd.c → drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
View File

@ -11,7 +11,7 @@
*/
#include "regs-mfc.h"
#include "s5p_mfc_cmd.h"
#include "s5p_mfc_cmd_v5.h"
#include "s5p_mfc_common.h"
#include "s5p_mfc_debug.h"

0
drivers/media/platform/s5p-mfc/s5p_mfc_cmd.h → drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.h
View File

2
drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
View File

@ -16,7 +16,7 @@
#include <linux/jiffies.h>
#include <linux/sched.h>
#include "regs-mfc.h"
#include "s5p_mfc_cmd.h"
#include "s5p_mfc_cmd_v5.h"
#include "s5p_mfc_common.h"
#include "s5p_mfc_debug.h"
#include "s5p_mfc_intr.h"

7
drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
View File

@ -28,9 +28,8 @@
#include "s5p_mfc_debug.h"
#include "s5p_mfc_dec.h"
#include "s5p_mfc_intr.h"
#include "s5p_mfc_opr.h"
#include "s5p_mfc_opr_v5.h"
#include "s5p_mfc_pm.h"
#include "s5p_mfc_shm.h"
static struct s5p_mfc_fmt formats[] = {
{
@ -695,10 +694,10 @@ static int vidioc_g_crop(struct file *file, void *priv,
return -EINVAL;
}
if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264) {
left = s5p_mfc_read_shm(ctx, CROP_INFO_H);
left = s5p_mfc_read_info_v5(ctx, CROP_INFO_H);
right = left >> S5P_FIMV_SHARED_CROP_RIGHT_SHIFT;
left = left & S5P_FIMV_SHARED_CROP_LEFT_MASK;
top = s5p_mfc_read_shm(ctx, CROP_INFO_V);
top = s5p_mfc_read_info_v5(ctx, CROP_INFO_V);
bottom = top >> S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT;
top = top & S5P_FIMV_SHARED_CROP_TOP_MASK;
cr->c.left = left;

2
drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
View File

@ -30,7 +30,7 @@
#include "s5p_mfc_debug.h"
#include "s5p_mfc_enc.h"
#include "s5p_mfc_intr.h"
#include "s5p_mfc_opr.h"
#include "s5p_mfc_opr_v5.h"
static struct s5p_mfc_fmt formats[] = {
{

103
drivers/media/platform/s5p-mfc/s5p_mfc_opr.c → drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c
View File

@ -13,14 +13,13 @@
*/
#include "regs-mfc.h"
#include "s5p_mfc_cmd.h"
#include "s5p_mfc_cmd_v5.h"
#include "s5p_mfc_common.h"
#include "s5p_mfc_ctrl.h"
#include "s5p_mfc_debug.h"
#include "s5p_mfc_intr.h"
#include "s5p_mfc_opr.h"
#include "s5p_mfc_opr_v5.h"
#include "s5p_mfc_pm.h"
#include "s5p_mfc_shm.h"
#include <asm/cacheflush.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
@ -262,12 +261,30 @@ int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx)
/* Zero content of the allocated memory */
memset(context_virt, 0, ctx->ctx_size);
wmb();
if (s5p_mfc_init_shm(ctx) < 0) {
vb2_dma_contig_memops.put(ctx->ctx_buf);
ctx->ctx_phys = 0;
ctx->ctx_buf = NULL;
/* Initialize shared memory */
ctx->shm_alloc = vb2_dma_contig_memops.alloc(
dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], SHARED_BUF_SIZE);
if (IS_ERR(ctx->shm_alloc)) {
mfc_err("failed to allocate shared memory\n");
return PTR_ERR(ctx->shm_alloc);
}
/* shared memory offset only keeps the offset from base (port a) */
ctx->shm_ofs = s5p_mfc_mem_cookie(
dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->shm_alloc)
- dev->bank1;
BUG_ON(ctx->shm_ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
ctx->shm = vb2_dma_contig_memops.vaddr(ctx->shm_alloc);
if (!ctx->shm) {
vb2_dma_contig_memops.put(ctx->shm_alloc);
ctx->shm_ofs = 0;
ctx->shm_alloc = NULL;
mfc_err("failed to virt addr of shared memory\n");
return -ENOMEM;
}
memset((void *)ctx->shm, 0, SHARED_BUF_SIZE);
wmb();
return 0;
}
@ -286,6 +303,20 @@ void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx)
}
}
void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data,
unsigned int ofs)
{
writel(data, (ctx->shm + ofs));
wmb();
}
unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx,
unsigned int ofs)
{
rmb();
return readl(ctx->shm + ofs);
}
/* Set registers for decoding temporary buffers */
void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
{
@ -311,7 +342,7 @@ int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
s5p_mfc_write_shm(ctx, start_num_byte, START_BYTE_NUM);
s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM);
return 0;
}
@ -438,10 +469,10 @@ int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx)
mfc_debug(2, "Not enough memory has been allocated\n");
return -ENOMEM;
}
s5p_mfc_write_shm(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
s5p_mfc_write_shm(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
s5p_mfc_write_info_v5(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC)
s5p_mfc_write_shm(ctx, frame_size_mv, ALLOC_MV_SIZE);
s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE);
mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK)
<< S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
S5P_FIMV_SI_CH0_INST_ID);
@ -685,16 +716,16 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
/* reaction coefficient */
if (p->rc_frame)
mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA);
shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
/* seq header ctrl */
shm &= ~(0x1 << 3);
shm |= (p->seq_hdr_mode << 3);
/* frame skip mode */
shm &= ~(0x3 << 1);
shm |= (p->frame_skip_mode << 1);
s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
/* fixed target bit */
s5p_mfc_write_shm(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
return 0;
}
@ -806,35 +837,35 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
}
if (!p->rc_frame &&
!p_264->rc_mb) {
shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
shm &= ~(0xFFF);
shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6);
shm |= (p_264->rc_p_frame_qp & 0x3F);
s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
}
/* extended encoder ctrl */
shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
/* AR VUI control */
shm &= ~(0x1 << 15);
shm |= (p_264->vui_sar << 1);
s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
if (p_264->vui_sar) {
/* aspect ration IDC */
shm = s5p_mfc_read_shm(ctx, SAMPLE_ASPECT_RATIO_IDC);
shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC);
shm &= ~(0xFF);
shm |= p_264->vui_sar_idc;
s5p_mfc_write_shm(ctx, shm, SAMPLE_ASPECT_RATIO_IDC);
s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC);
if (p_264->vui_sar_idc == 0xFF) {
/* sample AR info */
shm = s5p_mfc_read_shm(ctx, EXTENDED_SAR);
shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR);
shm &= ~(0xFFFFFFFF);
shm |= p_264->vui_ext_sar_width << 16;
shm |= p_264->vui_ext_sar_height;
s5p_mfc_write_shm(ctx, shm, EXTENDED_SAR);
s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR);
}
}
/* intra picture period for H.264 */
shm = s5p_mfc_read_shm(ctx, H264_I_PERIOD);
shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD);
/* control */
shm &= ~(0x1 << 16);
shm |= (p_264->open_gop << 16);
@ -843,16 +874,16 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
shm &= ~(0xFFFF);
shm |= p_264->open_gop_size;
}
s5p_mfc_write_shm(ctx, shm, H264_I_PERIOD);
s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD);
/* extended encoder ctrl */
shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
/* vbv buffer size */
if (p->frame_skip_mode ==
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
shm &= ~(0xFFFF << 16);
shm |= (p_264->cpb_size << 16);
}
s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
return 0;
}
@ -885,11 +916,11 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL);
/* qp */
if (!p->rc_frame) {
shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
shm &= ~(0xFFF);
shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6);
shm |= (p_mpeg4->rc_p_frame_qp & 0x3F);
s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
}
/* frame rate */
if (p->rc_frame) {
@ -898,12 +929,12 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
p->rc_framerate_denom;
mfc_write(dev, framerate,
S5P_FIMV_ENC_RC_FRAME_RATE);
shm = s5p_mfc_read_shm(ctx, RC_VOP_TIMING);
shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING);
shm &= ~(0xFFFFFFFF);
shm |= (1 << 31);
shm |= ((p->rc_framerate_num & 0x7FFF) << 16);
shm |= (p->rc_framerate_denom & 0xFFFF);
s5p_mfc_write_shm(ctx, shm, RC_VOP_TIMING);
s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING);
}
} else {
mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
@ -924,14 +955,14 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
reg |= p_mpeg4->rc_min_qp;
mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
/* extended encoder ctrl */
shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
/* vbv buffer size */
if (p->frame_skip_mode ==
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
shm &= ~(0xFFFF << 16);
shm |= (p->vbv_size << 16);
}
s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
return 0;
}
@ -946,10 +977,10 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
s5p_mfc_set_enc_params(ctx);
/* qp */
if (!p->rc_frame) {
shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP);
shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
shm &= ~(0xFFF);
shm |= (p_h263->rc_p_frame_qp & 0x3F);
s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP);
s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
}
/* frame rate */
if (p->rc_frame && p->rc_framerate_denom)
@ -973,14 +1004,14 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
reg |= p_h263->rc_min_qp;
mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
/* extended encoder ctrl */
shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL);
shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
/* vbv buffer size */
if (p->frame_skip_mode ==
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
shm &= ~(0xFFFF << 16);
shm |= (p->vbv_size << 16);
}
s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL);
s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
return 0;
}

70
drivers/media/platform/s5p-mfc/s5p_mfc_opr.h → drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.h
View File

@ -17,6 +17,69 @@
#include "s5p_mfc_common.h"
enum MFC_SHM_OFS {
EXTENEDED_DECODE_STATUS = 0x00, /* D */
SET_FRAME_TAG = 0x04, /* D */
GET_FRAME_TAG_TOP = 0x08, /* D */
GET_FRAME_TAG_BOT = 0x0C, /* D */
PIC_TIME_TOP = 0x10, /* D */
PIC_TIME_BOT = 0x14, /* D */
START_BYTE_NUM = 0x18, /* D */
CROP_INFO_H = 0x20, /* D */
CROP_INFO_V = 0x24, /* D */
EXT_ENC_CONTROL = 0x28, /* E */
ENC_PARAM_CHANGE = 0x2C, /* E */
RC_VOP_TIMING = 0x30, /* E, MPEG4 */
HEC_PERIOD = 0x34, /* E, MPEG4 */
METADATA_ENABLE = 0x38, /* C */
METADATA_STATUS = 0x3C, /* C */
METADATA_DISPLAY_INDEX = 0x40, /* C */
EXT_METADATA_START_ADDR = 0x44, /* C */
PUT_EXTRADATA = 0x48, /* C */
EXTRADATA_ADDR = 0x4C, /* C */
ALLOC_LUMA_DPB_SIZE = 0x64, /* D */
ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */
ALLOC_MV_SIZE = 0x6C, /* D */
P_B_FRAME_QP = 0x70, /* E */
SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
EXTENDED_SAR = 0x78, /* E, H.264, depned on
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
DISP_PIC_PROFILE = 0x7C, /* D */
FLUSH_CMD_TYPE = 0x80, /* C */
FLUSH_CMD_INBUF1 = 0x84, /* C */
FLUSH_CMD_INBUF2 = 0x88, /* C */
FLUSH_CMD_OUTBUF = 0x8C, /* E */
NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504)
depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */
RC_CONTROL_CONFIG = 0xA0, /* E */
BATCH_INPUT_ADDR = 0xA4, /* E */
BATCH_OUTPUT_ADDR = 0xA8, /* E */
BATCH_OUTPUT_SIZE = 0xAC, /* E */
MIN_LUMA_DPB_SIZE = 0xB0, /* D */
DEVICE_FORMAT_ID = 0xB4, /* C */
H264_POC_TYPE = 0xB8, /* D */
MIN_CHROMA_DPB_SIZE = 0xBC, /* D */
DISP_PIC_FRAME_TYPE = 0xC0, /* D */
FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */
ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */
EXTENDED_PAR = 0xCC, /* D, MPEG4 */
DBG_HISTORY_INPUT0 = 0xD0, /* C */
DBG_HISTORY_INPUT1 = 0xD4, /* C */
DBG_HISTORY_OUTPUT = 0xD8, /* C */
HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */
FRAME_PACK_SEI_ENABLE = 0x168, /* C */
FRAME_PACK_SEI_AVAIL = 0x16c, /* D */
FRAME_PACK_SEI_INFO = 0x17c, /* E */
};
int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx);
int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx);
@ -53,6 +116,13 @@ void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx);
void s5p_mfc_try_run(struct s5p_mfc_dev *dev);
void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
/* Shared memory ops */
void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data,
unsigned int ofs);
unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx,
unsigned int ofs);
#define s5p_mfc_get_dspl_y_adr() (readl(dev->regs_base + \
S5P_FIMV_SI_DISPLAY_Y_ADR) << \
MFC_OFFSET_SHIFT)

47
drivers/media/platform/s5p-mfc/s5p_mfc_shm.c
View File

@ -1,47 +0,0 @@
/*
* linux/drivers/media/platform/s5p-mfc/s5p_mfc_shm.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifdef CONFIG_ARCH_EXYNOS4
#include <linux/dma-mapping.h>
#endif
#include <linux/io.h>
#include "s5p_mfc_common.h"
#include "s5p_mfc_debug.h"
int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx)
{
struct s5p_mfc_dev *dev = ctx->dev;
void *shm_alloc_ctx = dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
ctx->shm_alloc = vb2_dma_contig_memops.alloc(shm_alloc_ctx,
SHARED_BUF_SIZE);
if (IS_ERR(ctx->shm_alloc)) {
mfc_err("failed to allocate shared memory\n");
return PTR_ERR(ctx->shm_alloc);
}
/* shm_ofs only keeps the offset from base (port a) */
ctx->shm_ofs = s5p_mfc_mem_cookie(shm_alloc_ctx, ctx->shm_alloc)
- dev->bank1;
BUG_ON(ctx->shm_ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
ctx->shm = vb2_dma_contig_memops.vaddr(ctx->shm_alloc);
if (!ctx->shm) {
vb2_dma_contig_memops.put(ctx->shm_alloc);
ctx->shm_ofs = 0;
ctx->shm_alloc = NULL;
mfc_err("failed to virt addr of shared memory\n");
return -ENOMEM;
}
memset((void *)ctx->shm, 0, SHARED_BUF_SIZE);
wmb();
return 0;
}

90
drivers/media/platform/s5p-mfc/s5p_mfc_shm.h
View File

@ -1,90 +0,0 @@
/*
* linux/drivers/media/platform/s5p-mfc/s5p_mfc_shm.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef S5P_MFC_SHM_H_
#define S5P_MFC_SHM_H_
enum MFC_SHM_OFS {
EXTENEDED_DECODE_STATUS = 0x00, /* D */
SET_FRAME_TAG = 0x04, /* D */
GET_FRAME_TAG_TOP = 0x08, /* D */
GET_FRAME_TAG_BOT = 0x0C, /* D */
PIC_TIME_TOP = 0x10, /* D */
PIC_TIME_BOT = 0x14, /* D */
START_BYTE_NUM = 0x18, /* D */
CROP_INFO_H = 0x20, /* D */
CROP_INFO_V = 0x24, /* D */
EXT_ENC_CONTROL = 0x28, /* E */
ENC_PARAM_CHANGE = 0x2C, /* E */
RC_VOP_TIMING = 0x30, /* E, MPEG4 */
HEC_PERIOD = 0x34, /* E, MPEG4 */
METADATA_ENABLE = 0x38, /* C */
METADATA_STATUS = 0x3C, /* C */
METADATA_DISPLAY_INDEX = 0x40, /* C */
EXT_METADATA_START_ADDR = 0x44, /* C */
PUT_EXTRADATA = 0x48, /* C */
EXTRADATA_ADDR = 0x4C, /* C */
ALLOC_LUMA_DPB_SIZE = 0x64, /* D */
ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */
ALLOC_MV_SIZE = 0x6C, /* D */
P_B_FRAME_QP = 0x70, /* E */
SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
EXTENDED_SAR = 0x78, /* E, H.264, depned on
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
DISP_PIC_PROFILE = 0x7C, /* D */
FLUSH_CMD_TYPE = 0x80, /* C */
FLUSH_CMD_INBUF1 = 0x84, /* C */
FLUSH_CMD_INBUF2 = 0x88, /* C */
FLUSH_CMD_OUTBUF = 0x8C, /* E */
NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504)
depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */
RC_CONTROL_CONFIG = 0xA0, /* E */
BATCH_INPUT_ADDR = 0xA4, /* E */
BATCH_OUTPUT_ADDR = 0xA8, /* E */
BATCH_OUTPUT_SIZE = 0xAC, /* E */
MIN_LUMA_DPB_SIZE = 0xB0, /* D */
DEVICE_FORMAT_ID = 0xB4, /* C */
H264_POC_TYPE = 0xB8, /* D */
MIN_CHROMA_DPB_SIZE = 0xBC, /* D */
DISP_PIC_FRAME_TYPE = 0xC0, /* D */
FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */
ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */
EXTENDED_PAR = 0xCC, /* D, MPEG4 */
DBG_HISTORY_INPUT0 = 0xD0, /* C */
DBG_HISTORY_INPUT1 = 0xD4, /* C */
DBG_HISTORY_OUTPUT = 0xD8, /* C */
HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */
};
int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
#define s5p_mfc_write_shm(ctx, x, ofs) \
do { \
writel(x, (ctx->shm + ofs)); \
wmb(); \
} while (0)
static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
{
rmb();
return readl(ctx->shm + ofs);
}
#endif /* S5P_MFC_SHM_H_ */