mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 00:39:33 +07:00
ath10k: enable pci soc powersaving
By using SOC_WAKE register it is possible to bring
down power consumption of QCA61X4 from 36mA to
16mA when associated and idle.
Currently the sleep threshold/grace period is at a
very conservative value of 60ms.
Contrary to QCA61X4 the QCA988X firmware doesn't
have Rx/beacon filtering available for client mode
and SWBA events are used for beaconing in AP/IBSS
so the SoC needs to be woken up at least every
~100ms in most cases. This means that QCA988X
is at a disadvantage and the power consumption
won't drop as much as for QCA61X4.
Due to putting irq-safe spinlocks on every MMIO
read/write it is expected this can cause a little
performance regression on some systems. I haven't
done any thorough measurements but some of my
tests don't show any extreme degradation.
The patch removes some explicit pci_wake calls
that were added in 320e14b8db51aa ("ath10k: fix
some pci wake/sleep issues"). This is safe because
all MMIO accesses are now wrapped and the device
is woken up automatically if necessary.
Signed-off-by: Michal Kazior <michal.kazior@tieto.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Michal Kazior
Kalle Valo
parent
917826be9f
commit
77258d409c
@ -36,6 +36,7 @@ enum ath10k_debug_mask {
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ATH10K_DBG_REGULATORY = 0x00000800,
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ATH10K_DBG_TESTMODE = 0x00001000,
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ATH10K_DBG_WMI_PRINT = 0x00002000,
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ATH10K_DBG_PCI_PS = 0x00004000,
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ATH10K_DBG_ANY = 0xffffffff,
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};
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@ -330,6 +330,205 @@ static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
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},
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};
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static bool ath10k_pci_is_awake(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
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RTC_STATE_ADDRESS);
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return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
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}
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static void __ath10k_pci_wake(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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lockdep_assert_held(&ar_pci->ps_lock);
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ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
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ar_pci->ps_wake_refcount, ar_pci->ps_awake);
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iowrite32(PCIE_SOC_WAKE_V_MASK,
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ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
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PCIE_SOC_WAKE_ADDRESS);
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}
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static void __ath10k_pci_sleep(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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lockdep_assert_held(&ar_pci->ps_lock);
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ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
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ar_pci->ps_wake_refcount, ar_pci->ps_awake);
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iowrite32(PCIE_SOC_WAKE_RESET,
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ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
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PCIE_SOC_WAKE_ADDRESS);
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ar_pci->ps_awake = false;
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}
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static int ath10k_pci_wake_wait(struct ath10k *ar)
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{
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int tot_delay = 0;
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int curr_delay = 5;
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while (tot_delay < PCIE_WAKE_TIMEOUT) {
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if (ath10k_pci_is_awake(ar))
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return 0;
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udelay(curr_delay);
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tot_delay += curr_delay;
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if (curr_delay < 50)
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curr_delay += 5;
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}
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return -ETIMEDOUT;
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}
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static int ath10k_pci_wake(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&ar_pci->ps_lock, flags);
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ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
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ar_pci->ps_wake_refcount, ar_pci->ps_awake);
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/* This function can be called very frequently. To avoid excessive
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* CPU stalls for MMIO reads use a cache var to hold the device state.
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*/
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if (!ar_pci->ps_awake) {
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__ath10k_pci_wake(ar);
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ret = ath10k_pci_wake_wait(ar);
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if (ret == 0)
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ar_pci->ps_awake = true;
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}
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if (ret == 0) {
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ar_pci->ps_wake_refcount++;
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WARN_ON(ar_pci->ps_wake_refcount == 0);
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}
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spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
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return ret;
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}
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static void ath10k_pci_sleep(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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unsigned long flags;
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spin_lock_irqsave(&ar_pci->ps_lock, flags);
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ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
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ar_pci->ps_wake_refcount, ar_pci->ps_awake);
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if (WARN_ON(ar_pci->ps_wake_refcount == 0))
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goto skip;
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ar_pci->ps_wake_refcount--;
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mod_timer(&ar_pci->ps_timer, jiffies +
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msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
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skip:
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spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
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}
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static void ath10k_pci_ps_timer(unsigned long ptr)
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{
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struct ath10k *ar = (void *)ptr;
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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unsigned long flags;
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spin_lock_irqsave(&ar_pci->ps_lock, flags);
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ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
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ar_pci->ps_wake_refcount, ar_pci->ps_awake);
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if (ar_pci->ps_wake_refcount > 0)
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goto skip;
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__ath10k_pci_sleep(ar);
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skip:
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spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
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}
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static void ath10k_pci_sleep_sync(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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unsigned long flags;
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del_timer_sync(&ar_pci->ps_timer);
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spin_lock_irqsave(&ar_pci->ps_lock, flags);
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WARN_ON(ar_pci->ps_wake_refcount > 0);
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__ath10k_pci_sleep(ar);
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spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
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}
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void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
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value, offset, ret);
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return;
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}
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iowrite32(value, ar_pci->mem + offset);
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ath10k_pci_sleep(ar);
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}
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u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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u32 val;
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
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offset, ret);
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return 0xffffffff;
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}
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val = ioread32(ar_pci->mem + offset);
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ath10k_pci_sleep(ar);
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return val;
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}
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u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
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{
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return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
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}
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void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
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{
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ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
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}
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u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
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{
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return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
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}
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void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
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{
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ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
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}
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static bool ath10k_pci_irq_pending(struct ath10k *ar)
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{
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u32 cause;
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@ -793,60 +992,6 @@ static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
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return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
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}
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static bool ath10k_pci_is_awake(struct ath10k *ar)
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{
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u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);
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return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
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}
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static int ath10k_pci_wake_wait(struct ath10k *ar)
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{
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int tot_delay = 0;
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int curr_delay = 5;
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while (tot_delay < PCIE_WAKE_TIMEOUT) {
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if (ath10k_pci_is_awake(ar))
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return 0;
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udelay(curr_delay);
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tot_delay += curr_delay;
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if (curr_delay < 50)
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curr_delay += 5;
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}
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return -ETIMEDOUT;
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}
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/* The rule is host is forbidden from accessing device registers while it's
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* asleep. Currently ath10k_pci_wake() and ath10k_pci_sleep() calls aren't
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* balanced and the device is kept awake all the time. This is intended for a
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* simpler solution for the following problems:
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*
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* * device can enter sleep during s2ram without the host knowing,
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*
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* * irq handlers access registers which is a problem if other device asserts
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* a shared irq line when ath10k is between hif_power_down() and
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* hif_power_up().
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*
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* FIXME: If power consumption is a concern (and there are *real* gains) then a
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* refcounted wake/sleep needs to be implemented.
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*/
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static int ath10k_pci_wake(struct ath10k *ar)
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{
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ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
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PCIE_SOC_WAKE_V_MASK);
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return ath10k_pci_wake_wait(ar);
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}
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static void ath10k_pci_sleep(struct ath10k *ar)
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{
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ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
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PCIE_SOC_WAKE_RESET);
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}
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/* Called by lower (CE) layer when a send to Target completes. */
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static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
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{
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@ -1348,6 +1493,9 @@ static void ath10k_pci_flush(struct ath10k *ar)
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static void ath10k_pci_hif_stop(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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unsigned long flags;
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
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/* Most likely the device has HTT Rx ring configured. The only way to
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@ -1366,6 +1514,10 @@ static void ath10k_pci_hif_stop(struct ath10k *ar)
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ath10k_pci_irq_disable(ar);
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ath10k_pci_irq_sync(ar);
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ath10k_pci_flush(ar);
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spin_lock_irqsave(&ar_pci->ps_lock, flags);
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WARN_ON(ar_pci->ps_wake_refcount > 0);
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spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
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}
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static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
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@ -1990,12 +2142,6 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_err(ar, "failed to wake up target: %d\n", ret);
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return ret;
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}
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pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
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&ar_pci->link_ctl);
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pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
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@ -2047,7 +2193,6 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
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ath10k_pci_ce_deinit(ar);
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err_sleep:
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ath10k_pci_sleep(ar);
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return ret;
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}
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@ -2064,7 +2209,12 @@ static void ath10k_pci_hif_power_down(struct ath10k *ar)
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static int ath10k_pci_hif_suspend(struct ath10k *ar)
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{
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ath10k_pci_sleep(ar);
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/* The grace timer can still be counting down and ar->ps_awake be true.
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* It is known that the device may be asleep after resuming regardless
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* of the SoC powersave state before suspending. Hence make sure the
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* device is asleep before proceeding.
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*/
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ath10k_pci_sleep_sync(ar);
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return 0;
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}
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@ -2074,13 +2224,6 @@ static int ath10k_pci_hif_resume(struct ath10k *ar)
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct pci_dev *pdev = ar_pci->pdev;
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u32 val;
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_err(ar, "failed to wake device up on resume: %d\n", ret);
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return ret;
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}
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/* Suspend/Resume resets the PCI configuration space, so we have to
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* re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
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@ -2091,7 +2234,7 @@ static int ath10k_pci_hif_resume(struct ath10k *ar)
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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return ret;
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return 0;
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}
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#endif
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@ -2185,13 +2328,6 @@ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
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{
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struct ath10k *ar = arg;
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
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return IRQ_NONE;
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}
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if (ar_pci->num_msi_intrs == 0) {
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if (!ath10k_pci_irq_pending(ar))
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@ -2638,8 +2774,12 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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pdev->subsystem_vendor, pdev->subsystem_device);
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spin_lock_init(&ar_pci->ce_lock);
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spin_lock_init(&ar_pci->ps_lock);
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setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
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(unsigned long)ar);
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setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
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(unsigned long)ar);
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ret = ath10k_pci_claim(ar);
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if (ret) {
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@ -2647,12 +2787,6 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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goto err_core_destroy;
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}
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ret = ath10k_pci_wake(ar);
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if (ret) {
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ath10k_err(ar, "failed to wake up: %d\n", ret);
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goto err_release;
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}
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ret = ath10k_pci_alloc_pipes(ar);
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if (ret) {
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ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
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@ -2716,9 +2850,6 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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ath10k_pci_free_pipes(ar);
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err_sleep:
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ath10k_pci_sleep(ar);
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err_release:
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ath10k_pci_release(ar);
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err_core_destroy:
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@ -2748,6 +2879,7 @@ static void ath10k_pci_remove(struct pci_dev *pdev)
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ath10k_pci_deinit_irq(ar);
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ath10k_pci_ce_deinit(ar);
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ath10k_pci_free_pipes(ar);
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ath10k_pci_sleep_sync(ar);
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ath10k_pci_release(ar);
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ath10k_core_destroy(ar);
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}
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@ -191,6 +191,35 @@ struct ath10k_pci {
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* device bootup is executed and re-programmed later.
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*/
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u16 link_ctl;
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/* Protects ps_awake and ps_wake_refcount */
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spinlock_t ps_lock;
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/* The device has a special powersave-oriented register. When device is
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* considered asleep it drains less power and driver is forbidden from
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* accessing most MMIO registers. If host were to access them without
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* waking up the device might scribble over host memory or return
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* 0xdeadbeef readouts.
|
||||
*/
|
||||
unsigned long ps_wake_refcount;
|
||||
|
||||
/* Waking up takes some time (up to 2ms in some cases) so it can be bad
|
||||
* for latency. To mitigate this the device isn't immediately allowed
|
||||
* to sleep after all references are undone - instead there's a grace
|
||||
* period after which the powersave register is updated unless some
|
||||
* activity to/from device happened in the meantime.
|
||||
*
|
||||
* Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
|
||||
*/
|
||||
struct timer_list ps_timer;
|
||||
|
||||
/* MMIO registers are used to communicate with the device. With
|
||||
* intensive traffic accessing powersave register would be a bit
|
||||
* wasteful overhead and would needlessly stall CPU. It is far more
|
||||
* efficient to rely on a variable in RAM and update it only upon
|
||||
* powersave register state changes.
|
||||
*/
|
||||
bool ps_awake;
|
||||
};
|
||||
|
||||
static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
|
||||
@ -215,61 +244,25 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
|
||||
* for this device; but that's not guaranteed.
|
||||
*/
|
||||
#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
|
||||
(((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
|
||||
(((ath10k_pci_read32(ar, (SOC_CORE_BASE_ADDRESS | \
|
||||
CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
|
||||
0x100000 | ((addr) & 0xfffff))
|
||||
|
||||
/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
|
||||
#define DIAG_ACCESS_CE_TIMEOUT_MS 10
|
||||
|
||||
/* Target exposes its registers for direct access. However before host can
|
||||
* access them it needs to make sure the target is awake (ath10k_pci_wake,
|
||||
* ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
|
||||
* to sleep unless host tells it to (ath10k_pci_sleep).
|
||||
*
|
||||
* If host tries to access target registers without waking it up it can
|
||||
* scribble over host memory.
|
||||
*
|
||||
* If target is asleep waking it up may take up to even 2ms.
|
||||
void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
|
||||
void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
|
||||
void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
|
||||
|
||||
u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
|
||||
u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
|
||||
u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
|
||||
|
||||
/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
|
||||
* frequently. To avoid this put SoC to sleep after a very conservative grace
|
||||
* period. Adjust with great care.
|
||||
*/
|
||||
|
||||
static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
|
||||
u32 value)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
|
||||
iowrite32(value, ar_pci->mem + offset);
|
||||
}
|
||||
|
||||
static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
|
||||
return ioread32(ar_pci->mem + offset);
|
||||
}
|
||||
|
||||
static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
|
||||
{
|
||||
return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
|
||||
}
|
||||
|
||||
static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
|
||||
{
|
||||
ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
|
||||
}
|
||||
|
||||
static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
|
||||
return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
|
||||
}
|
||||
|
||||
static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
|
||||
iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
|
||||
}
|
||||
#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
|
||||
|
||||
#endif /* _PCI_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user