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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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rtw88: 8821c: add basic functions
RTL8821CE chipsets are 802.11ac dual-band WiFi + BT combo chips. This patch adds the basic functions such as parameter tables, chip information, power on flow. Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Tzu-En Huang <tehuang@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200616091625.26489-2-yhchuang@realtek.com
This commit is contained in:
Tzu-En Huang
Kalle Valo
parent
cce0e08301
commit
769a29ce2a
@ -183,6 +183,7 @@ enum rtw_chip_type {
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RTW_CHIP_TYPE_8822B,
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RTW_CHIP_TYPE_8822C,
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RTW_CHIP_TYPE_8723D,
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RTW_CHIP_TYPE_8821C,
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};
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enum rtw_tx_queue_type {
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@ -43,6 +43,8 @@
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#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
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#define BITS_PLL 0xf0
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#define REG_AFE_XTAL_CTRL 0x24
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#define REG_AFE_PLL_CTRL 0x28
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#define REG_AFE_CTRL3 0x2c
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#define BIT_MASK_XTAL 0x00FFF000
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#define BIT_XTAL_GMP_BIT4 BIT(28)
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@ -476,6 +478,8 @@
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#define REG_RFE_CTRL_E 0x0974
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#define REG_2ND_CCA_CTRL 0x0976
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#define REG_CCK0_FAREPORT 0xa2c
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#define REG_DIS_DPD 0x0a70
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#define DIS_DPD_MASK GENMASK(9, 0)
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#define DIS_DPD_RATE6M BIT(0)
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651
drivers/net/wireless/realtek/rtw88/rtw8821c.c
Normal file
651
drivers/net/wireless/realtek/rtw88/rtw8821c.c
Normal file
@ -0,0 +1,651 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#include "main.h"
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#include "coex.h"
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#include "fw.h"
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#include "tx.h"
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#include "rx.h"
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#include "phy.h"
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#include "rtw8821c.h"
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#include "rtw8821c_table.h"
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#include "mac.h"
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#include "reg.h"
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#include "debug.h"
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#include "bf.h"
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static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
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struct rtw8821c_efuse *map)
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{
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ether_addr_copy(efuse->addr, map->e.mac_addr);
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}
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static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
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{
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struct rtw_efuse *efuse = &rtwdev->efuse;
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struct rtw8821c_efuse *map;
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int i;
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map = (struct rtw8821c_efuse *)log_map;
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efuse->rfe_option = map->rfe_option;
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efuse->rf_board_option = map->rf_board_option;
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efuse->crystal_cap = map->xtal_k;
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efuse->pa_type_2g = map->pa_type;
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efuse->pa_type_5g = map->pa_type;
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efuse->lna_type_2g = map->lna_type_2g[0];
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efuse->lna_type_5g = map->lna_type_5g[0];
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efuse->channel_plan = map->channel_plan;
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efuse->country_code[0] = map->country_code[0];
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efuse->country_code[1] = map->country_code[1];
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efuse->bt_setting = map->rf_bt_setting;
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efuse->regd = map->rf_board_option & 0x7;
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efuse->thermal_meter[0] = map->thermal_meter;
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efuse->thermal_meter_k = map->thermal_meter;
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efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
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efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
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for (i = 0; i < 4; i++)
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efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
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switch (rtw_hci_type(rtwdev)) {
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case RTW_HCI_TYPE_PCIE:
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rtw8821ce_efuse_parsing(efuse, map);
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break;
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default:
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/* unsupported now */
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return -ENOTSUPP;
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}
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return 0;
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}
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static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
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{
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u8 crystal_cap, val;
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/* power on BB/RF domain */
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val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
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val |= BIT_FEN_PCIEA;
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rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
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/* toggle BB reset */
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val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
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rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
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val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
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rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
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val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
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rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
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rtw_write8(rtwdev, REG_RF_CTRL,
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BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
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usleep_range(10, 11);
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rtw_write8(rtwdev, REG_WLRF1 + 3,
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BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
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usleep_range(10, 11);
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/* pre init before header files config */
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rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
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rtw_phy_load_tables(rtwdev);
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crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
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rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
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rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
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rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
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/* post init after header files config */
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rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
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rtw_phy_init(rtwdev);
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}
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static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
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{
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u32 value32;
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u16 pre_txcnt;
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/* protocol configuration */
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rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
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rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
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pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
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rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
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rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
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value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
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(WLAN_MAX_AGG_PKT_LIMIT << 16) |
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(WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
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rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
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rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
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WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
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rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
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rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
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rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
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rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
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rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
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/* EDCA configuration */
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rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
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rtw_write16(rtwdev, REG_TXPAUSE, 0);
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rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
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rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
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rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
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rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
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rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
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rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
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rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
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/* Set beacon cotnrol - enable TSF and other related functions */
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rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
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/* Set send beacon related registers */
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rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
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rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
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rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
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rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
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/* WMAC configuration */
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rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
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rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
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rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
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rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
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rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
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rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
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rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
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rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
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rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6));
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rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
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rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
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return 0;
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}
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static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
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{
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u8 ldo_pwr;
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ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
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ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
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rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
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}
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static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
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{0x0086,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_SDIO_MSK,
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RTW_PWR_ADDR_SDIO,
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RTW_PWR_CMD_WRITE, BIT(0), 0},
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{0x0086,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_SDIO_MSK,
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RTW_PWR_ADDR_SDIO,
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RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
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{0x004A,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_USB_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), 0},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
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{0x0300,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, 0xFF, 0},
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{0x0301,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, 0xFF, 0},
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{0xFFFF,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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0,
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RTW_PWR_CMD_END, 0, 0},
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};
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static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
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{0x0020,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
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{0x0001,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
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{0x0000,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(5), 0},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
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{0x0075,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
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{0x0006,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
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{0x0075,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), 0},
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{0x0006,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(7), 0},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
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{0x10C3,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_USB_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
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{0x0005,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_POLLING, BIT(0), 0},
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{0x0020,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
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{0x0074,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
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{0x0022,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(1), 0},
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{0x0062,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
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(BIT(7) | BIT(6) | BIT(5))},
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{0x0061,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_PCI_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
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{0x007C,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(1), 0},
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{0xFFFF,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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0,
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RTW_PWR_CMD_END, 0, 0},
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};
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static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
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{0x0093,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
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RTW_PWR_ADDR_MAC,
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RTW_PWR_CMD_WRITE, BIT(3), 0},
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{0x001F,
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RTW_PWR_CUT_ALL_MSK,
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RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0},
|
||||
{0x0049,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(1), 0},
|
||||
{0x0006,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
|
||||
{0x0002,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(1), 0},
|
||||
{0x10C3,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(0), 0},
|
||||
{0x0005,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
|
||||
{0x0005,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_POLLING, BIT(1), 0},
|
||||
{0x0020,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(3), 0},
|
||||
{0x0000,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
|
||||
{0xFFFF,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
0,
|
||||
RTW_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
|
||||
{0x0007,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0x20},
|
||||
{0x0067,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(5), 0},
|
||||
{0x0005,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_PCI_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
|
||||
{0x004A,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(0), 0},
|
||||
{0x0067,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(5), 0},
|
||||
{0x0067,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(4), 0},
|
||||
{0x004F,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(0), 0},
|
||||
{0x0067,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(1), 0},
|
||||
{0x0046,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
|
||||
{0x0067,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(2), 0},
|
||||
{0x0046,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
|
||||
{0x0062,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
|
||||
{0x0081,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
|
||||
{0x0005,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
|
||||
{0x0086,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
|
||||
{0x0086,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_POLLING, BIT(1), 0},
|
||||
{0x0090,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
|
||||
RTW_PWR_ADDR_MAC,
|
||||
RTW_PWR_CMD_WRITE, BIT(1), 0},
|
||||
{0x0044,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0},
|
||||
{0x0040,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0x90},
|
||||
{0x0041,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0x00},
|
||||
{0x0042,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_SDIO_MSK,
|
||||
RTW_PWR_ADDR_SDIO,
|
||||
RTW_PWR_CMD_WRITE, 0xFF, 0x04},
|
||||
{0xFFFF,
|
||||
RTW_PWR_CUT_ALL_MSK,
|
||||
RTW_PWR_INTF_ALL_MSK,
|
||||
0,
|
||||
RTW_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
|
||||
trans_carddis_to_cardemu_8821c,
|
||||
trans_cardemu_to_act_8821c,
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
|
||||
trans_act_to_cardemu_8821c,
|
||||
trans_cardemu_to_carddis_8821c,
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct rtw_intf_phy_para usb2_param_8821c[] = {
|
||||
{0xFFFF, 0x00,
|
||||
RTW_IP_SEL_PHY,
|
||||
RTW_INTF_PHY_CUT_ALL,
|
||||
RTW_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
static const struct rtw_intf_phy_para usb3_param_8821c[] = {
|
||||
{0xFFFF, 0x0000,
|
||||
RTW_IP_SEL_PHY,
|
||||
RTW_INTF_PHY_CUT_ALL,
|
||||
RTW_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
|
||||
{0x0009, 0x6380,
|
||||
RTW_IP_SEL_PHY,
|
||||
RTW_INTF_PHY_CUT_ALL,
|
||||
RTW_INTF_PHY_PLATFORM_ALL},
|
||||
{0xFFFF, 0x0000,
|
||||
RTW_IP_SEL_PHY,
|
||||
RTW_INTF_PHY_CUT_ALL,
|
||||
RTW_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
|
||||
{0xFFFF, 0x0000,
|
||||
RTW_IP_SEL_PHY,
|
||||
RTW_INTF_PHY_CUT_ALL,
|
||||
RTW_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
|
||||
.usb2_para = usb2_param_8821c,
|
||||
.usb3_para = usb3_param_8821c,
|
||||
.gen1_para = pcie_gen1_param_8821c,
|
||||
.gen2_para = pcie_gen2_param_8821c,
|
||||
.n_usb2_para = ARRAY_SIZE(usb2_param_8821c),
|
||||
.n_usb3_para = ARRAY_SIZE(usb2_param_8821c),
|
||||
.n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c),
|
||||
.n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c),
|
||||
};
|
||||
|
||||
static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
|
||||
[0] = RTW_DEF_RFE(8821c, 0, 0),
|
||||
};
|
||||
|
||||
static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
|
||||
.ctrl = LTECOEX_ACCESS_CTRL,
|
||||
.wdata = LTECOEX_WRITE_DATA,
|
||||
.rdata = LTECOEX_READ_DATA,
|
||||
};
|
||||
|
||||
static struct rtw_page_table page_table_8821c[] = {
|
||||
/* not sure what [0] stands for */
|
||||
{16, 16, 16, 14, 1},
|
||||
{16, 16, 16, 14, 1},
|
||||
{16, 16, 0, 0, 1},
|
||||
{16, 16, 16, 0, 1},
|
||||
{16, 16, 16, 14, 1},
|
||||
};
|
||||
|
||||
static struct rtw_rqpn rqpn_table_8821c[] = {
|
||||
/* not sure what [0] stands for */
|
||||
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
|
||||
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
|
||||
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
|
||||
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
|
||||
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
|
||||
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
|
||||
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
|
||||
RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
|
||||
RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
|
||||
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
|
||||
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
|
||||
RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
|
||||
{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
|
||||
RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
|
||||
RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
|
||||
};
|
||||
|
||||
static struct rtw_prioq_addrs prioq_addrs_8821c = {
|
||||
.prio[RTW_DMA_MAPPING_EXTRA] = {
|
||||
.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
|
||||
},
|
||||
.prio[RTW_DMA_MAPPING_LOW] = {
|
||||
.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
|
||||
},
|
||||
.prio[RTW_DMA_MAPPING_NORMAL] = {
|
||||
.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
|
||||
},
|
||||
.prio[RTW_DMA_MAPPING_HIGH] = {
|
||||
.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
|
||||
},
|
||||
.wsize = true,
|
||||
};
|
||||
|
||||
static struct rtw_chip_ops rtw8821c_ops = {
|
||||
.phy_set_param = rtw8821c_phy_set_param,
|
||||
.read_efuse = rtw8821c_read_efuse,
|
||||
.mac_init = rtw8821c_mac_init,
|
||||
.read_rf = rtw_phy_read_rf,
|
||||
.write_rf = rtw_phy_write_rf_reg_sipi,
|
||||
.set_antenna = NULL,
|
||||
.cfg_ldo25 = rtw8821c_cfg_ldo25,
|
||||
};
|
||||
|
||||
struct rtw_chip_info rtw8821c_hw_spec = {
|
||||
.ops = &rtw8821c_ops,
|
||||
.id = RTW_CHIP_TYPE_8821C,
|
||||
.fw_name = "rtw88/rtw8821c_fw.bin",
|
||||
.wlan_cpu = RTW_WCPU_11AC,
|
||||
.tx_pkt_desc_sz = 48,
|
||||
.tx_buf_desc_sz = 16,
|
||||
.rx_pkt_desc_sz = 24,
|
||||
.rx_buf_desc_sz = 8,
|
||||
.phy_efuse_size = 512,
|
||||
.log_efuse_size = 512,
|
||||
.ptct_efuse_size = 96,
|
||||
.txff_size = 65536,
|
||||
.rxff_size = 16384,
|
||||
.txgi_factor = 1,
|
||||
.is_pwr_by_rate_dec = true,
|
||||
.max_power_index = 0x3f,
|
||||
.csi_buf_pg_num = 0,
|
||||
.band = RTW_BAND_2G | RTW_BAND_5G,
|
||||
.page_size = 128,
|
||||
.ht_supported = true,
|
||||
.vht_supported = true,
|
||||
.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
|
||||
.sys_func_en = 0xD8,
|
||||
.pwr_on_seq = card_enable_flow_8821c,
|
||||
.pwr_off_seq = card_disable_flow_8821c,
|
||||
.page_table = page_table_8821c,
|
||||
.rqpn_table = rqpn_table_8821c,
|
||||
.prioq_addrs = &prioq_addrs_8821c,
|
||||
.intf_table = &phy_para_table_8821c,
|
||||
.rf_base_addr = {0x2800, 0x2c00},
|
||||
.rf_sipi_addr = {0xc90, 0xe90},
|
||||
.ltecoex_addr = &rtw8821c_ltecoex_addr,
|
||||
.mac_tbl = &rtw8821c_mac_tbl,
|
||||
.agc_tbl = &rtw8821c_agc_tbl,
|
||||
.bb_tbl = &rtw8821c_bb_tbl,
|
||||
.rf_tbl = {&rtw8821c_rf_a_tbl},
|
||||
.rfe_defs = rtw8821c_rfe_defs,
|
||||
.rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
|
||||
.rx_ldpc = false,
|
||||
};
|
||||
EXPORT_SYMBOL(rtw8821c_hw_spec);
|
||||
|
||||
MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
|
||||
|
||||
MODULE_AUTHOR("Realtek Corporation");
|
||||
MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
188
drivers/net/wireless/realtek/rtw88/rtw8821c.h
Normal file
188
drivers/net/wireless/realtek/rtw88/rtw8821c.h
Normal file
@ -0,0 +1,188 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/* Copyright(c) 2018-2019 Realtek Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RTW8821C_H__
|
||||
#define __RTW8821C_H__
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define RCR_VHT_ACK BIT(26)
|
||||
|
||||
struct rtw8821ce_efuse {
|
||||
u8 mac_addr[ETH_ALEN]; /* 0xd0 */
|
||||
u8 vender_id[2];
|
||||
u8 device_id[2];
|
||||
u8 sub_vender_id[2];
|
||||
u8 sub_device_id[2];
|
||||
u8 pmc[2];
|
||||
u8 exp_device_cap[2];
|
||||
u8 msi_cap;
|
||||
u8 ltr_cap; /* 0xe3 */
|
||||
u8 exp_link_control[2];
|
||||
u8 link_cap[4];
|
||||
u8 link_control[2];
|
||||
u8 serial_number[8];
|
||||
u8 res0:2; /* 0xf4 */
|
||||
u8 ltr_en:1;
|
||||
u8 res1:2;
|
||||
u8 obff:2;
|
||||
u8 res2:3;
|
||||
u8 obff_cap:2;
|
||||
u8 res3:4;
|
||||
u8 res4[3];
|
||||
u8 class_code[3];
|
||||
u8 pci_pm_L1_2_supp:1;
|
||||
u8 pci_pm_L1_1_supp:1;
|
||||
u8 aspm_pm_L1_2_supp:1;
|
||||
u8 aspm_pm_L1_1_supp:1;
|
||||
u8 L1_pm_substates_supp:1;
|
||||
u8 res5:3;
|
||||
u8 port_common_mode_restore_time;
|
||||
u8 port_t_power_on_scale:2;
|
||||
u8 res6:1;
|
||||
u8 port_t_power_on_value:5;
|
||||
u8 res7;
|
||||
};
|
||||
|
||||
struct rtw8821c_efuse {
|
||||
__le16 rtl_id;
|
||||
u8 res0[0x0e];
|
||||
|
||||
/* power index for four RF paths */
|
||||
struct rtw_txpwr_idx txpwr_idx_table[4];
|
||||
|
||||
u8 channel_plan; /* 0xb8 */
|
||||
u8 xtal_k;
|
||||
u8 thermal_meter;
|
||||
u8 iqk_lck;
|
||||
u8 pa_type; /* 0xbc */
|
||||
u8 lna_type_2g[2]; /* 0xbd */
|
||||
u8 lna_type_5g[2];
|
||||
u8 rf_board_option;
|
||||
u8 rf_feature_option;
|
||||
u8 rf_bt_setting;
|
||||
u8 eeprom_version;
|
||||
u8 eeprom_customer_id;
|
||||
u8 tx_bb_swing_setting_2g;
|
||||
u8 tx_bb_swing_setting_5g;
|
||||
u8 tx_pwr_calibrate_rate;
|
||||
u8 rf_antenna_option; /* 0xc9 */
|
||||
u8 rfe_option;
|
||||
u8 country_code[2];
|
||||
u8 res[3];
|
||||
union {
|
||||
struct rtw8821ce_efuse e;
|
||||
};
|
||||
};
|
||||
|
||||
static inline void
|
||||
_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
|
||||
{
|
||||
/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
|
||||
rtw_write32_mask(rtwdev, addr, mask, data);
|
||||
rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
|
||||
}
|
||||
|
||||
#define rtw_write32s_mask(rtwdev, addr, mask, data) \
|
||||
do { \
|
||||
BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
|
||||
\
|
||||
_rtw_write32s_mask(rtwdev, addr, mask, data); \
|
||||
} while (0)
|
||||
|
||||
#define BIT_FEN_PCIEA BIT(6)
|
||||
#define WLAN_SLOT_TIME 0x09
|
||||
#define WLAN_PIFS_TIME 0x19
|
||||
#define WLAN_SIFS_CCK_CONT_TX 0xA
|
||||
#define WLAN_SIFS_OFDM_CONT_TX 0xE
|
||||
#define WLAN_SIFS_CCK_TRX 0x10
|
||||
#define WLAN_SIFS_OFDM_TRX 0x10
|
||||
#define WLAN_VO_TXOP_LIMIT 0x186
|
||||
#define WLAN_VI_TXOP_LIMIT 0x3BC
|
||||
#define WLAN_RDG_NAV 0x05
|
||||
#define WLAN_TXOP_NAV 0x1B
|
||||
#define WLAN_CCK_RX_TSF 0x30
|
||||
#define WLAN_OFDM_RX_TSF 0x30
|
||||
#define WLAN_TBTT_PROHIBIT 0x04
|
||||
#define WLAN_TBTT_HOLD_TIME 0x064
|
||||
#define WLAN_DRV_EARLY_INT 0x04
|
||||
#define WLAN_BCN_DMA_TIME 0x02
|
||||
|
||||
#define WLAN_RX_FILTER0 0x0FFFFFFF
|
||||
#define WLAN_RX_FILTER2 0xFFFF
|
||||
#define WLAN_RCR_CFG 0xE400220E
|
||||
#define WLAN_RXPKT_MAX_SZ 12288
|
||||
#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
|
||||
|
||||
#define WLAN_AMPDU_MAX_TIME 0x70
|
||||
#define WLAN_RTS_LEN_TH 0xFF
|
||||
#define WLAN_RTS_TX_TIME_TH 0x08
|
||||
#define WLAN_MAX_AGG_PKT_LIMIT 0x20
|
||||
#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
|
||||
#define FAST_EDCA_VO_TH 0x06
|
||||
#define FAST_EDCA_VI_TH 0x06
|
||||
#define FAST_EDCA_BE_TH 0x06
|
||||
#define FAST_EDCA_BK_TH 0x06
|
||||
#define WLAN_BAR_RETRY_LIMIT 0x01
|
||||
#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
|
||||
|
||||
#define WLAN_TX_FUNC_CFG1 0x30
|
||||
#define WLAN_TX_FUNC_CFG2 0x30
|
||||
#define WLAN_MAC_OPT_NORM_FUNC1 0x98
|
||||
#define WLAN_MAC_OPT_LB_FUNC1 0x80
|
||||
#define WLAN_MAC_OPT_FUNC2 0x30810041
|
||||
|
||||
#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
|
||||
(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
|
||||
(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
|
||||
(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
|
||||
|
||||
#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
|
||||
(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
|
||||
|
||||
#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
|
||||
#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
|
||||
#define WLAN_PRE_TXCNT_TIME_TH 0x1E4
|
||||
|
||||
#define REG_INIRTS_RATE_SEL 0x0480
|
||||
#define REG_HTSTFWT 0x800
|
||||
#define REG_RXPSEL 0x808
|
||||
#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
|
||||
#define REG_TXPSEL 0x80c
|
||||
#define REG_RXCCAMSK 0x814
|
||||
#define REG_CCASEL 0x82c
|
||||
#define REG_PDMFTH 0x830
|
||||
#define REG_CCA2ND 0x838
|
||||
#define REG_L1WT 0x83c
|
||||
#define REG_L1PKWT 0x840
|
||||
#define REG_MRC 0x850
|
||||
#define REG_CLKTRK 0x860
|
||||
#define REG_ADCCLK 0x8ac
|
||||
#define REG_ADC160 0x8c4
|
||||
#define REG_ADC40 0x8c8
|
||||
#define REG_CDDTXP 0x93c
|
||||
#define REG_TXPSEL1 0x940
|
||||
#define REG_ACBB0 0x948
|
||||
#define REG_ACBBRXFIR 0x94c
|
||||
#define REG_ACGG2TBL 0x958
|
||||
#define REG_RXSB 0xa00
|
||||
#define REG_ADCINI 0xa04
|
||||
#define REG_TXSF2 0xa24
|
||||
#define REG_TXSF6 0xa28
|
||||
#define REG_RXDESC 0xa2c
|
||||
#define REG_ENTXCCK 0xa80
|
||||
#define REG_AGCTR_A 0xc08
|
||||
#define REG_TXDFIR 0xc20
|
||||
#define REG_RXIGI_A 0xc50
|
||||
#define REG_TRSW 0xca0
|
||||
#define REG_RFESEL0 0xcb0
|
||||
#define REG_RFESEL8 0xcb4
|
||||
#define REG_RFECTL 0xcb8
|
||||
#define REG_RFEINV 0xcbc
|
||||
#define REG_AGCTR_B 0xe08
|
||||
#define REG_RXIGI_B 0xe50
|
||||
#define REG_ANTWT 0x1904
|
||||
#define REG_IQKFAILMSK 0x1bf0
|
||||
|
||||
#endif
|
||||
6611
drivers/net/wireless/realtek/rtw88/rtw8821c_table.c
Normal file
6611
drivers/net/wireless/realtek/rtw88/rtw8821c_table.c
Normal file
File diff suppressed because it is too large
Load Diff
15
drivers/net/wireless/realtek/rtw88/rtw8821c_table.h
Normal file
15
drivers/net/wireless/realtek/rtw88/rtw8821c_table.h
Normal file
@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/* Copyright(c) 2018-2019 Realtek Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RTW8821C_TABLE_H__
|
||||
#define __RTW8821C_TABLE_H__
|
||||
|
||||
extern const struct rtw_table rtw8821c_mac_tbl;
|
||||
extern const struct rtw_table rtw8821c_agc_tbl;
|
||||
extern const struct rtw_table rtw8821c_bb_tbl;
|
||||
extern const struct rtw_table rtw8821c_bb_pg_type0_tbl;
|
||||
extern const struct rtw_table rtw8821c_rf_a_tbl;
|
||||
extern const struct rtw_table rtw8821c_txpwr_lmt_type0_tbl;
|
||||
|
||||
#endif
|
||||
30
drivers/net/wireless/realtek/rtw88/rtw8821ce.c
Normal file
30
drivers/net/wireless/realtek/rtw88/rtw8821ce.c
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/* Copyright(c) 2018-2019 Realtek Corporation
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include "rtw8821ce.h"
|
||||
|
||||
static const struct pci_device_id rtw_8821ce_id_table[] = {
|
||||
{
|
||||
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xC821),
|
||||
.driver_data = (kernel_ulong_t)&rtw8821c_hw_spec
|
||||
},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, rtw_8821ce_id_table);
|
||||
|
||||
static struct pci_driver rtw_8821ce_driver = {
|
||||
.name = "rtw_8821ce",
|
||||
.id_table = rtw_8821ce_id_table,
|
||||
.probe = rtw_pci_probe,
|
||||
.remove = rtw_pci_remove,
|
||||
.driver.pm = &rtw_pm_ops,
|
||||
.shutdown = rtw_pci_shutdown,
|
||||
};
|
||||
module_pci_driver(rtw_8821ce_driver);
|
||||
|
||||
MODULE_AUTHOR("Realtek Corporation");
|
||||
MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821ce driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
14
drivers/net/wireless/realtek/rtw88/rtw8821ce.h
Normal file
14
drivers/net/wireless/realtek/rtw88/rtw8821ce.h
Normal file
@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
|
||||
/* Copyright(c) 2018-2019 Realtek Corporation
|
||||
*/
|
||||
|
||||
#ifndef __RTW_8821CE_H_
|
||||
#define __RTW_8821CE_H_
|
||||
|
||||
extern const struct dev_pm_ops rtw_pm_ops;
|
||||
extern struct rtw_chip_info rtw8821c_hw_spec;
|
||||
int rtw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
|
||||
void rtw_pci_remove(struct pci_dev *pdev);
|
||||
void rtw_pci_shutdown(struct pci_dev *pdev);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user