mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 04:06:53 +07:00
intelfb: make i915 modeset
This takes the modeset and pll code from my X driver. Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Dave Airlie
parent
9639d5ec07
commit
7679f4d692
@ -562,6 +562,8 @@ intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
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static int calc_vclock3(int index, int m, int n, int p)
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{
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if (p == 0 || n == 0)
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return 0;
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return PLL_REFCLK * m / n / p;
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}
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@ -570,6 +572,8 @@ static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
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switch(index)
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{
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case PLLS_I9xx:
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if (p1 == 0)
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return 0;
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return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1)) * (p2 ? 10 : 5)));
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case PLLS_I8xx:
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@ -779,8 +783,20 @@ splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
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if (index == PLLS_I9xx)
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{
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p1 = (p / 10) + 1;
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p2 = 0;
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switch (p) {
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case 10:
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p1 = 2;
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p2 = 0;
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break;
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case 20:
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p1 = 1;
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p2 = 0;
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break;
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default:
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p1 = (p / 10) + 1;
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p2 = 0;
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break;
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}
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*retp1 = (unsigned int)p1;
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*retp2 = (unsigned int)p2;
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@ -813,8 +829,8 @@ static int
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calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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u32 *retp2, u32 *retclock)
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{
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u32 m1, m2, n, p1, p2, n1;
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u32 f_vco, p, p_best = 0, m, f_out;
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u32 m1, m2, n, p1, p2, n1, testm;
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u32 f_vco, p, p_best = 0, m, f_out = 0;
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u32 err_max, err_target, err_best = 10000000;
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u32 n_best = 0, m_best = 0, f_best, f_err;
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u32 p_min, p_max, p_inc, div_min, div_max;
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@ -826,7 +842,10 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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DBG_MSG("Clock is %d\n", clock);
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div_max = plls[index].max_vco_freq / clock;
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div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
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if (index == PLLS_I9xx)
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div_min = 5;
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else
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div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
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if (clock <= plls[index].p_transition_clock)
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p_inc = plls[index].p_inc_lo;
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@ -839,6 +858,16 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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if (p_max > plls[index].max_p)
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p_max = plls[index].max_p;
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if (clock < PLL_REFCLK && index==PLLS_I9xx)
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{
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p_min = 10;
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p_max = 20;
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/* this makes 640x480 work it really shouldn't
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- SOMEONE WITHOUT DOCS WOZ HERE */
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if (clock < 30000)
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clock *= 4;
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}
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DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
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p = p_min;
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@ -854,26 +883,28 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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do {
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m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
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if (m < plls[index].min_m)
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m = plls[index].min_m;
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m = plls[index].min_m + 1;
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if (m > plls[index].max_m)
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m = plls[index].max_m;
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f_out = calc_vclock3(index, m, n, p);
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if (splitm(index, m, &m1, &m2)) {
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WRN_MSG("cannot split m = %d\n", m);
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n++;
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continue;
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}
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if (clock > f_out)
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f_err = clock - f_out;
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else
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f_err = f_out - clock;
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if (f_err < err_best) {
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m_best = m;
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n_best = n;
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p_best = p;
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f_best = f_out;
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err_best = f_err;
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m = plls[index].max_m - 1;
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for (testm = m - 1; testm <= m; testm++) {
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f_out = calc_vclock3(index, m, n, p);
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if (splitm(index, m, &m1, &m2)) {
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WRN_MSG("cannot split m = %d\n", m);
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n++;
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continue;
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}
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if (clock > f_out)
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f_err = clock - f_out;
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else/* slightly bias the error for bigger clocks */
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f_err = f_out - clock + 1;
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if (f_err < err_best) {
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m_best = m;
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n_best = n;
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p_best = p;
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f_best = f_out;
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err_best = f_err;
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}
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}
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n++;
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} while ((n <= plls[index].max_n) && (f_out >= clock));
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@ -1157,6 +1188,7 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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u32 hsync_reg, htotal_reg, hblank_reg;
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u32 vsync_reg, vtotal_reg, vblank_reg;
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u32 src_size_reg;
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u32 count, tmp_val[3];
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/* Assume single pipe, display plane A, analog CRT. */
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@ -1225,6 +1257,28 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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src_size_reg = SRC_SIZE_A;
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}
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/* turn off pipe */
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tmp = INREG(pipe_conf_reg);
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tmp &= ~PIPECONF_ENABLE;
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OUTREG(pipe_conf_reg, tmp);
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count = 0;
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do{
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tmp_val[count%3] = INREG(0x70000);
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if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
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break;
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count++;
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udelay(1);
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if (count % 200 == 0)
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{
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tmp = INREG(pipe_conf_reg);
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tmp &= ~PIPECONF_ENABLE;
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OUTREG(pipe_conf_reg, tmp);
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}
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} while(count < 2000);
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OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
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/* Disable planes A and B. */
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tmp = INREG(DSPACNTR);
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tmp &= ~DISPPLANE_PLANE_ENABLE;
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@ -1242,10 +1296,8 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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tmp |= ADPA_DPMS_D3;
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OUTREG(ADPA, tmp);
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/* turn off pipe */
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tmp = INREG(pipe_conf_reg);
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tmp &= ~PIPECONF_ENABLE;
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OUTREG(pipe_conf_reg, tmp);
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/* do some funky magic - xyzzy */
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OUTREG(0x61204, 0xabcd0000);
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/* turn off PLL */
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tmp = INREG(dpll_reg);
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@ -1257,6 +1309,22 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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OUTREG(fp0_reg, *fp0);
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OUTREG(fp1_reg, *fp1);
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/* Enable PLL */
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tmp = INREG(dpll_reg);
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tmp |= DPLL_VCO_ENABLE;
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OUTREG(dpll_reg, tmp);
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/* Set DVOs B/C */
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OUTREG(DVOB, hw->dvob);
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OUTREG(DVOC, hw->dvoc);
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/* undo funky magic */
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OUTREG(0x61204, 0x00000000);
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/* Set ADPA */
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OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
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OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
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/* Set pipe parameters */
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OUTREG(hsync_reg, *hs);
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OUTREG(hblank_reg, *hb);
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@ -1266,18 +1334,6 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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OUTREG(vtotal_reg, *vt);
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OUTREG(src_size_reg, *ss);
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/* Set DVOs B/C */
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OUTREG(DVOB, hw->dvob);
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OUTREG(DVOC, hw->dvoc);
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/* Set ADPA */
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OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
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/* Enable PLL */
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tmp = INREG(dpll_reg);
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tmp |= DPLL_VCO_ENABLE;
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OUTREG(dpll_reg, tmp);
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/* Enable pipe */
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OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
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