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ARM: dts: sunxi: Use macros for references to CCU clocks

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A few clocks from the CCU were exported later, and references to them in
the device tree were using raw numbers.

Now that the DT binding header changes are in as well, switch to the
macros for more clarity.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This commit is contained in:
Chen-Yu Tsai 2020-01-06 16:59:33 +08:00 committed by Maxime Ripard
parent 60d0426d76
commit 765866edb1
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
4 changed files with 9 additions and 8 deletions
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2
arch/arm/boot/dts/sun5i.dtsi
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@ -185,7 +185,7 @@ ve_sram: sram-section@0 {
mbus: dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
clocks = <&ccu 99>;
clocks = <&ccu CLK_MBUS>;
dma-ranges = <0x00000000 0x40000000 0x20000000>;
#interconnect-cells = <1>;
};

6
arch/arm/boot/dts/sun8i-a83t.dtsi
View File

@ -1006,9 +1006,9 @@ emac: ethernet@1c30000 {
reg = <0x01c30000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu 13>;
resets = <&ccu CLK_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu 27>;
clocks = <&ccu RST_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
@ -1102,7 +1102,7 @@ r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
<&ccu 6>;
<&ccu CLK_PLL_PERIPH>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;

2
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -995,7 +995,7 @@ hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-r40-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
<&ccu 7>, <&ccu 16>;
<&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
clock-names = "bus", "mod", "pll-0", "pll-1";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";

7
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -559,7 +559,7 @@ external_mdio: mdio@2 {
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-h3-mbus";
reg = <0x01c62000 0x1000>;
clocks = <&ccu 113>;
clocks = <&ccu CLK_MBUS>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
#interconnect-cells = <1>;
};
@ -817,7 +817,7 @@ hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun8i-h3-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu 6>;
<&ccu CLK_PLL_VIDEO>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@ -837,7 +837,8 @@ rtc: rtc@1f00000 {
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;