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Merge tag 'drm-intel-fixes-2016-04-21' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Hi Dave, fixes all around, all but one are cc: stable material, the most important ones are likely the Skylake hang fixes from Mika. * tag 'drm-intel-fixes-2016-04-21' of git://anongit.freedesktop.org/drm-intel: drm/i915: Use fw_domains_put_with_fifo() on HSW drm/i915: Force ringbuffers to not be at offset 0 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write drm/i915/skl: Fix spurious gpu hang with gt3/gt4 revs drm/i915/skl: Fix rc6 based gpu/system hang drm/i915/userptr: Hold mmref whilst calling get-user-pages drm/i915: Fixup the free space logic in ring_prepare drm/i915/skl+: Use plane size for relative data rate calculation
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commit
762ce44589
@ -2634,8 +2634,9 @@ struct drm_i915_cmd_table {
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
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((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
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IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
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IS_SKL_GT3(dev) || \
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IS_SKL_GT4(dev))
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/*
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* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
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* even when in MSI mode. This results in spurious interrupt warnings if the
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@ -501,19 +501,24 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
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if (pvec != NULL) {
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struct mm_struct *mm = obj->userptr.mm->mm;
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down_read(&mm->mmap_sem);
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while (pinned < npages) {
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ret = get_user_pages_remote(work->task, mm,
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obj->userptr.ptr + pinned * PAGE_SIZE,
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npages - pinned,
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!obj->userptr.read_only, 0,
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pvec + pinned, NULL);
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if (ret < 0)
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break;
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ret = -EFAULT;
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if (atomic_inc_not_zero(&mm->mm_users)) {
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down_read(&mm->mmap_sem);
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while (pinned < npages) {
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ret = get_user_pages_remote
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(work->task, mm,
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obj->userptr.ptr + pinned * PAGE_SIZE,
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npages - pinned,
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!obj->userptr.read_only, 0,
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pvec + pinned, NULL);
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if (ret < 0)
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break;
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pinned += ret;
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pinned += ret;
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}
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up_read(&mm->mmap_sem);
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mmput(mm);
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}
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up_read(&mm->mmap_sem);
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}
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mutex_lock(&dev->struct_mutex);
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@ -841,11 +841,11 @@ static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
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if (unlikely(total_bytes > remain_usable)) {
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/*
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* The base request will fit but the reserved space
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* falls off the end. So only need to to wait for the
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* reserved size after flushing out the remainder.
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* falls off the end. So don't need an immediate wrap
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* and only need to effectively wait for the reserved
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* size space from the start of ringbuffer.
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*/
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wait_bytes = remain_actual + ringbuf->reserved_size;
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need_wrap = true;
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} else if (total_bytes > ringbuf->space) {
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/* No wrapping required, just waiting. */
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wait_bytes = total_bytes;
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@ -1913,15 +1913,18 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
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struct intel_ringbuffer *ringbuf = request->ringbuf;
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int ret;
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ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS);
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ret = intel_logical_ring_begin(request, 8 + WA_TAIL_DWORDS);
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if (ret)
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return ret;
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/* We're using qword write, seqno should be aligned to 8 bytes. */
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BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
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/* w/a for post sync ops following a GPGPU operation we
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* need a prior CS_STALL, which is emitted by the flush
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* following the batch.
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*/
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intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5));
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intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
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intel_logical_ring_emit(ringbuf,
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(PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_CS_STALL |
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@ -1929,7 +1932,10 @@ static int gen8_emit_request_render(struct drm_i915_gem_request *request)
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intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring));
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
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/* We're thrashing one dword of HWS. */
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
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intel_logical_ring_emit(ringbuf, MI_NOOP);
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return intel_logical_ring_advance_and_submit(request);
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}
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@ -2876,25 +2876,28 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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const struct drm_plane_state *pstate,
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int y)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
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struct drm_framebuffer *fb = pstate->fb;
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uint32_t width = 0, height = 0;
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width = drm_rect_width(&intel_pstate->src) >> 16;
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height = drm_rect_height(&intel_pstate->src) >> 16;
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if (intel_rotation_90_or_270(pstate->rotation))
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swap(width, height);
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/* for planar format */
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if (fb->pixel_format == DRM_FORMAT_NV12) {
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if (y) /* y-plane data rate */
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return intel_crtc->config->pipe_src_w *
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intel_crtc->config->pipe_src_h *
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return width * height *
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drm_format_plane_cpp(fb->pixel_format, 0);
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else /* uv-plane data rate */
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return (intel_crtc->config->pipe_src_w/2) *
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(intel_crtc->config->pipe_src_h/2) *
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return (width / 2) * (height / 2) *
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drm_format_plane_cpp(fb->pixel_format, 1);
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}
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/* for packed formats */
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return intel_crtc->config->pipe_src_w *
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intel_crtc->config->pipe_src_h *
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drm_format_plane_cpp(fb->pixel_format, 0);
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return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
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}
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/*
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@ -2973,8 +2976,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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struct drm_framebuffer *fb = plane->state->fb;
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int id = skl_wm_plane_id(intel_plane);
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if (fb == NULL)
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if (!to_intel_plane_state(plane->state)->visible)
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continue;
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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continue;
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@ -3000,7 +3004,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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uint16_t plane_blocks, y_plane_blocks = 0;
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int id = skl_wm_plane_id(intel_plane);
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if (pstate->fb == NULL)
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if (!to_intel_plane_state(pstate)->visible)
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continue;
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if (plane->type == DRM_PLANE_TYPE_CURSOR)
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continue;
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@ -3123,26 +3127,36 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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{
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struct drm_plane *plane = &intel_plane->base;
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struct drm_framebuffer *fb = plane->state->fb;
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struct intel_plane_state *intel_pstate =
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to_intel_plane_state(plane->state);
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uint32_t latency = dev_priv->wm.skl_latency[level];
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uint32_t method1, method2;
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uint32_t plane_bytes_per_line, plane_blocks_per_line;
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uint32_t res_blocks, res_lines;
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uint32_t selected_result;
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uint8_t cpp;
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uint32_t width = 0, height = 0;
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if (latency == 0 || !cstate->base.active || !fb)
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if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
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return false;
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width = drm_rect_width(&intel_pstate->src) >> 16;
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height = drm_rect_height(&intel_pstate->src) >> 16;
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if (intel_rotation_90_or_270(plane->state->rotation))
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swap(width, height);
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cpp = drm_format_plane_cpp(fb->pixel_format, 0);
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method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
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cpp, latency);
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method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
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cstate->base.adjusted_mode.crtc_htotal,
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cstate->pipe_src_w,
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cpp, fb->modifier[0],
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width,
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cpp,
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fb->modifier[0],
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latency);
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plane_bytes_per_line = cstate->pipe_src_w * cpp;
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plane_bytes_per_line = width * cpp;
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plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
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if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
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@ -968,7 +968,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
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/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
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tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
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if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
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if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
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IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
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tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
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WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
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@ -1085,7 +1085,8 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
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WA_SET_BIT_MASKED(HIZ_CHICKEN,
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BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
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if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
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/* This is tied to WaForceContextSaveRestoreNonCoherent */
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if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
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/*
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*Use Force Non-Coherent whenever executing a 3D context. This
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* is a workaround for a possible hang in the unlikely event
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@ -2090,10 +2091,12 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_gem_object *obj = ringbuf->obj;
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/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
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unsigned flags = PIN_OFFSET_BIAS | 4096;
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int ret;
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if (HAS_LLC(dev_priv) && !obj->stolen) {
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ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
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ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
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if (ret)
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return ret;
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@ -2109,7 +2112,8 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
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return -ENOMEM;
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}
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} else {
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ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
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ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
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flags | PIN_MAPPABLE);
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if (ret)
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return ret;
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@ -2454,11 +2458,11 @@ static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
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if (unlikely(total_bytes > remain_usable)) {
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/*
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* The base request will fit but the reserved space
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* falls off the end. So only need to to wait for the
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* reserved size after flushing out the remainder.
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* falls off the end. So don't need an immediate wrap
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* and only need to effectively wait for the reserved
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* size space from the start of ringbuffer.
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*/
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wait_bytes = remain_actual + ringbuf->reserved_size;
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need_wrap = true;
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} else if (total_bytes > ringbuf->space) {
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/* No wrapping required, just waiting. */
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wait_bytes = total_bytes;
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@ -1189,7 +1189,11 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
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} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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dev_priv->uncore.funcs.force_wake_get =
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fw_domains_get_with_thread_status;
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dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
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if (IS_HASWELL(dev))
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dev_priv->uncore.funcs.force_wake_put =
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fw_domains_put_with_fifo;
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else
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dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
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fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
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FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
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} else if (IS_IVYBRIDGE(dev)) {
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