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drm/amdgpu: add ih ip block for sienna_cichlid

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Update IH handling for sienna_cichlid

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2019-06-16 22:37:56 +08:00 committed by Alex Deucher
parent 0b3df16b5a
commit 757b3af8ec
2 changed files with 18 additions and 4 deletions
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21
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
View File

@ -34,6 +34,9 @@
#define MAX_REARM_RETRY 10
#define mmIH_CHICKEN_Sienna_Cichlid 0x018d
#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0
static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
/**
@ -265,10 +268,20 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
if (ih->use_bus_addr) {
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
break;
default:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
break;
}
}
}

1
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -486,6 +486,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
return -EINVAL;