mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 07:20:53 +07:00
clk: ti: Drop legacy clk-3xxx-legacy code
We have now had omap3 booting in device tree only mode for a while and all this code is unused. Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
ffb009b243
commit
7558562a70
@ -19,10 +19,6 @@ obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
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clk-dra7-atl.o dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
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ifdef CONFIG_ATAGS
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obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
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endif
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endif # CONFIG_ARCH_OMAP2PLUS
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obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o
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File diff suppressed because it is too large
Load Diff
@ -336,141 +336,6 @@ void ti_dt_clk_init_retry_clks(void)
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}
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}
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
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{
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while (*patch) {
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memcpy((*patch)->patch, *patch, sizeof(**patch));
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patch++;
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}
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}
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struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
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{
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struct clk *clk;
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struct ti_clk_fixed *fixed;
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struct ti_clk_fixed_factor *fixed_factor;
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struct clk_hw *clk_hw;
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int ret;
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if (setup->clk)
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return setup->clk;
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switch (setup->type) {
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case TI_CLK_FIXED:
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fixed = setup->data;
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clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0,
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fixed->frequency);
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if (!IS_ERR(clk)) {
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ret = ti_clk_add_alias(NULL, clk, setup->name);
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if (ret) {
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clk_unregister(clk);
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clk = ERR_PTR(ret);
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}
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}
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break;
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case TI_CLK_MUX:
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clk = ti_clk_register_mux(setup);
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break;
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case TI_CLK_DIVIDER:
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clk = ti_clk_register_divider(setup);
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break;
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case TI_CLK_COMPOSITE:
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clk = ti_clk_register_composite(setup);
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break;
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case TI_CLK_FIXED_FACTOR:
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fixed_factor = setup->data;
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clk = clk_register_fixed_factor(NULL, setup->name,
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fixed_factor->parent,
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0, fixed_factor->mult,
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fixed_factor->div);
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if (!IS_ERR(clk)) {
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ret = ti_clk_add_alias(NULL, clk, setup->name);
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if (ret) {
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clk_unregister(clk);
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clk = ERR_PTR(ret);
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}
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}
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break;
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case TI_CLK_GATE:
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clk = ti_clk_register_gate(setup);
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break;
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case TI_CLK_DPLL:
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clk = ti_clk_register_dpll(setup);
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break;
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default:
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pr_err("bad type for %s!\n", setup->name);
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clk = ERR_PTR(-EINVAL);
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}
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if (!IS_ERR(clk)) {
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setup->clk = clk;
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if (setup->clkdm_name) {
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clk_hw = __clk_get_hw(clk);
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if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
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pr_warn("can't setup clkdm for basic clk %s\n",
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setup->name);
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} else {
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to_clk_hw_omap(clk_hw)->clkdm_name =
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setup->clkdm_name;
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omap2_init_clk_clkdm(clk_hw);
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}
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}
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}
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return clk;
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}
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int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
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{
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struct clk *clk;
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bool retry;
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struct ti_clk_alias *retry_clk;
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struct ti_clk_alias *tmp;
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while (clks->clk) {
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clk = ti_clk_register_clk(clks->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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list_add(&clks->link, &retry_list);
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} else {
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pr_err("register for %s failed: %ld\n",
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clks->clk->name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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}
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clks++;
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}
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retry = true;
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while (!list_empty(&retry_list) && retry) {
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retry = false;
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list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
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pr_debug("retry-init: %s\n", retry_clk->clk->name);
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clk = ti_clk_register_clk(retry_clk->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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continue;
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} else {
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pr_err("register for %s failed: %ld\n",
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retry_clk->clk->name,
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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} else {
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retry = true;
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list_del(&retry_clk->link);
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}
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}
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}
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return 0;
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}
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#endif
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static const struct of_device_id simple_clk_match_table[] __initconst = {
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{ .compatible = "fixed-clock" },
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{ .compatible = "fixed-factor-clock" },
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@ -92,17 +92,6 @@ struct ti_clk {
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struct clk *clk;
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};
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struct ti_clk_alias {
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struct ti_clk *clk;
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struct clk_lookup lk;
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struct list_head link;
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};
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struct ti_clk_fixed {
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u32 frequency;
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u16 flags;
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};
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struct ti_clk_mux {
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u8 bit_shift;
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int num_parents;
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@ -123,13 +112,6 @@ struct ti_clk_divider {
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u16 flags;
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};
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struct ti_clk_fixed_factor {
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const char *parent;
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u16 div;
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u16 mult;
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u16 flags;
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};
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struct ti_clk_gate {
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const char *parent;
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u8 bit_shift;
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@ -138,44 +120,6 @@ struct ti_clk_gate {
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u16 flags;
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};
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struct ti_clk_composite {
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struct ti_clk_divider *divider;
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struct ti_clk_mux *mux;
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struct ti_clk_gate *gate;
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u16 flags;
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};
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struct ti_clk_clkdm_gate {
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const char *parent;
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u16 flags;
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};
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struct ti_clk_dpll {
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int num_parents;
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u16 control_reg;
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u16 idlest_reg;
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u16 autoidle_reg;
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u16 mult_div1_reg;
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u8 module;
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const char **parents;
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u16 flags;
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u8 modes;
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u32 mult_mask;
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u32 div1_mask;
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u32 enable_mask;
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u32 autoidle_mask;
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u32 freqsel_mask;
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u32 idlest_mask;
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u32 dco_mask;
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u32 sddiv_mask;
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u16 max_multiplier;
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u16 max_divider;
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u8 min_divider;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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};
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/* Composite clock component types */
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enum {
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CLK_COMPONENT_TYPE_GATE = 0,
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@ -237,29 +181,17 @@ extern const struct omap_clkctrl_data omap4_clkctrl_data[];
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typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
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struct clk *ti_clk_register_gate(struct ti_clk *setup);
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struct clk *ti_clk_register_interface(struct ti_clk *setup);
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struct clk *ti_clk_register_mux(struct ti_clk *setup);
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struct clk *ti_clk_register_divider(struct ti_clk *setup);
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struct clk *ti_clk_register_composite(struct ti_clk *setup);
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struct clk *ti_clk_register_dpll(struct ti_clk *setup);
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struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
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const char *con);
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int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
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void ti_clk_add_aliases(void);
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struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
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struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
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struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
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int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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u8 flags, u8 *width,
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const struct clk_div_table **table);
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void ti_clk_patch_legacy_clks(struct ti_clk **patch);
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struct clk *ti_clk_register_clk(struct ti_clk *setup);
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int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
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int ti_clk_get_reg_addr(struct device_node *node, int index,
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struct clk_omap_reg *reg);
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void ti_dt_clocks_register(struct ti_dt_clk *oclks);
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@ -116,51 +116,6 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
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#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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struct clk *ti_clk_register_composite(struct ti_clk *setup)
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{
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struct ti_clk_composite *comp;
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struct clk_hw *gate;
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struct clk_hw *mux;
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struct clk_hw *div;
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int num_parents = 1;
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const char * const *parent_names = NULL;
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struct clk *clk;
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int ret;
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comp = setup->data;
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div = ti_clk_build_component_div(comp->divider);
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gate = ti_clk_build_component_gate(comp->gate);
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mux = ti_clk_build_component_mux(comp->mux);
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if (div)
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parent_names = &comp->divider->parent;
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if (gate)
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parent_names = &comp->gate->parent;
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if (mux) {
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num_parents = comp->mux->num_parents;
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parent_names = comp->mux->parents;
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}
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clk = clk_register_composite(NULL, setup->name,
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parent_names, num_parents, mux,
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&ti_clk_mux_ops, div,
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&ti_composite_divider_ops, gate,
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&ti_composite_gate_ops, 0);
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ret = ti_clk_add_alias(NULL, clk, setup->name);
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if (ret) {
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clk_unregister(clk);
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return ERR_PTR(ret);
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}
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return clk;
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}
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#endif
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static void __init _register_composite(void *user,
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struct device_node *node)
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{
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@ -203,96 +203,6 @@ static void __init _register_dpll(void *user,
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kfree(clk_hw);
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}
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg)
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{
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reg->index = module;
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reg->offset = offset;
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}
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struct clk *ti_clk_register_dpll(struct ti_clk *setup)
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{
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struct clk_hw_omap *clk_hw;
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struct clk_init_data init = { NULL };
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struct dpll_data *dd;
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struct clk *clk;
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struct ti_clk_dpll *dpll;
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const struct clk_ops *ops = &omap3_dpll_ck_ops;
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struct clk *clk_ref;
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struct clk *clk_bypass;
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dpll = setup->data;
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if (dpll->num_parents < 2)
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return ERR_PTR(-EINVAL);
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clk_ref = clk_get_sys(NULL, dpll->parents[0]);
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clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
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if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
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return ERR_PTR(-EAGAIN);
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dd = kzalloc(sizeof(*dd), GFP_KERNEL);
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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if (!dd || !clk_hw) {
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clk = ERR_PTR(-ENOMEM);
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goto cleanup;
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}
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clk_hw->dpll_data = dd;
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clk_hw->ops = &clkhwops_omap3_dpll;
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clk_hw->hw.init = &init;
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init.name = setup->name;
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init.ops = ops;
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init.num_parents = dpll->num_parents;
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init.parent_names = dpll->parents;
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_get_reg(dpll->module, dpll->control_reg, &dd->control_reg);
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_get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg);
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_get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg);
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_get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg);
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dd->modes = dpll->modes;
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dd->div1_mask = dpll->div1_mask;
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dd->idlest_mask = dpll->idlest_mask;
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dd->mult_mask = dpll->mult_mask;
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dd->autoidle_mask = dpll->autoidle_mask;
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dd->enable_mask = dpll->enable_mask;
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dd->sddiv_mask = dpll->sddiv_mask;
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dd->dco_mask = dpll->dco_mask;
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dd->max_divider = dpll->max_divider;
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dd->min_divider = dpll->min_divider;
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dd->max_multiplier = dpll->max_multiplier;
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dd->auto_recal_bit = dpll->auto_recal_bit;
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dd->recal_en_bit = dpll->recal_en_bit;
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dd->recal_st_bit = dpll->recal_st_bit;
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dd->clk_ref = __clk_get_hw(clk_ref);
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dd->clk_bypass = __clk_get_hw(clk_bypass);
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if (dpll->flags & CLKF_CORE)
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ops = &omap3_dpll_core_ck_ops;
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if (dpll->flags & CLKF_PER)
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ops = &omap3_dpll_per_ck_ops;
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if (dpll->flags & CLKF_J_TYPE)
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dd->flags |= DPLL_J_TYPE;
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clk = ti_clk_register(NULL, &clk_hw->hw, setup->name);
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if (!IS_ERR(clk))
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return clk;
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cleanup:
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kfree(dd);
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kfree(clk_hw);
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return clk;
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
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defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
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defined(CONFIG_SOC_AM43XX)
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@ -128,53 +128,6 @@ static struct clk *_register_gate(struct device *dev, const char *name,
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return clk;
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}
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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struct clk *ti_clk_register_gate(struct ti_clk *setup)
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{
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const struct clk_ops *ops = &omap_gate_clk_ops;
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const struct clk_hw_omap_ops *hw_ops = NULL;
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struct clk_omap_reg reg;
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u32 flags = 0;
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u8 clk_gate_flags = 0;
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struct ti_clk_gate *gate;
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gate = setup->data;
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if (gate->flags & CLKF_INTERFACE)
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return ti_clk_register_interface(setup);
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if (gate->flags & CLKF_SET_RATE_PARENT)
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flags |= CLK_SET_RATE_PARENT;
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if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
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clk_gate_flags |= INVERT_ENABLE;
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if (gate->flags & CLKF_HSDIV) {
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ops = &omap_gate_clk_hsdiv_restore_ops;
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hw_ops = &clkhwops_wait;
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}
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if (gate->flags & CLKF_DSS)
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hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
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if (gate->flags & CLKF_WAIT)
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hw_ops = &clkhwops_wait;
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if (gate->flags & CLKF_CLKDM)
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ops = &omap_gate_clkdm_clk_ops;
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if (gate->flags & CLKF_AM35XX)
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hw_ops = &clkhwops_am35xx_ipss_module_wait;
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reg.index = gate->module;
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reg.offset = gate->reg;
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reg.ptr = NULL;
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return _register_gate(NULL, setup->name, gate->parent, flags,
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®, gate->bit_shift,
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clk_gate_flags, ops, hw_ops);
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}
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struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
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{
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struct clk_hw_omap *gate;
|
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@ -204,7 +157,6 @@ struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
|
||||
|
||||
return &gate->hw;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
|
||||
@ -67,38 +67,6 @@ static struct clk *_register_interface(struct device *dev, const char *name,
|
||||
return clk;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
|
||||
struct clk *ti_clk_register_interface(struct ti_clk *setup)
|
||||
{
|
||||
const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
|
||||
struct clk_omap_reg reg;
|
||||
struct ti_clk_gate *gate;
|
||||
|
||||
gate = setup->data;
|
||||
reg.index = gate->module;
|
||||
reg.offset = gate->reg;
|
||||
reg.ptr = NULL;
|
||||
|
||||
if (gate->flags & CLKF_NO_WAIT)
|
||||
ops = &clkhwops_iclk;
|
||||
|
||||
if (gate->flags & CLKF_HSOTGUSB)
|
||||
ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
|
||||
if (gate->flags & CLKF_DSS)
|
||||
ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
|
||||
if (gate->flags & CLKF_SSI)
|
||||
ops = &clkhwops_omap3430es2_iclk_ssi_wait;
|
||||
|
||||
if (gate->flags & CLKF_AM35XX)
|
||||
ops = &clkhwops_am35xx_ipss_wait;
|
||||
|
||||
return _register_interface(NULL, setup->name, gate->parent,
|
||||
®, gate->bit_shift, ops);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user