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drm/amdgpu: make function names consistent in nbio files

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All functions should have nbio_v* prefix.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2017-12-08 11:39:49 -05:00
parent 1cb4ca5968
commit 74e1d67c73
2 changed files with 16 additions and 16 deletions
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16
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
View File

@ -212,22 +212,22 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
*flags |= AMD_CG_SUPPORT_BIF_LS;
}
static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
}
static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
}
static u32 get_pcie_index_offset(struct amdgpu_device *adev)
static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
}
static u32 get_pcie_data_offset(struct amdgpu_device *adev)
static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
}
@ -248,10 +248,10 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
};
const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
.get_hdp_flush_req_offset = get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = get_hdp_flush_done_offset,
.get_pcie_index_offset = get_pcie_index_offset,
.get_pcie_data_offset = get_pcie_data_offset,
.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
};

16
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
View File

@ -182,22 +182,22 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev)
WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}
static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
}
static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
}
static u32 get_pcie_index_offset(struct amdgpu_device *adev)
static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
}
static u32 get_pcie_data_offset(struct amdgpu_device *adev)
static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
}
@ -218,9 +218,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
};
const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
.get_hdp_flush_req_offset = get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = get_hdp_flush_done_offset,
.get_pcie_index_offset = get_pcie_index_offset,
.get_pcie_data_offset = get_pcie_data_offset,
.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
.get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
.get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
};