ARM: shmobile: r8a7791: Add MMP clock to device tree

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Yoshifumi Hosoya 2014-10-14 16:01:43 +09:00 committed by Simon Horman
parent 4ba8f2468c
commit 74d89d25f6
2 changed files with 20 additions and 9 deletions

View File

@ -977,18 +977,23 @@ mstp0_clks: mstp0_clks@e6150130 {
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&m2_clk>, <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
<&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
<&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
<&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_3DG
R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
R8A7791_CLK_VSP1_S
>;
clock-output-names =
"jpu", "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0",
"vsp1-du1", "vsp1-du0", "vsp1-sy";
"vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
"2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
"tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";

View File

@ -25,9 +25,15 @@
#define R8A7791_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_VCP0 1
#define R8A7791_CLK_VPC0 3
#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_SSP1 9
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_3DG 12
#define R8A7791_CLK_2DDMAC 15
#define R8A7791_CLK_FDP1_1 18
#define R8A7791_CLK_FDP1_0 19
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
#define R8A7791_CLK_CMT0 24