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drm/amd/display: update predefined latency for Rv1_F0

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Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2017-08-01 13:23:56 -04:00 committed by Alex Deucher
parent a7b06724ee
commit 746e082fdd
2 changed files with 13 additions and 0 deletions
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10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
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@ -1323,6 +1323,13 @@ static bool construct(
dc->dcn_ip = dcn10_ip_defaults; dc->dcn_ip = dcn10_ip_defaults;
dc->dcn_soc = dcn10_soc_defaults; dc->dcn_soc = dcn10_soc_defaults;
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc->dcn_soc.urgent_latency = 3;
dc->public.debug.disable_dmcu = true;
dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
}
dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
ASSERT(dc->dcn_soc.number_of_channels < 3); ASSERT(dc->dcn_soc.number_of_channels < 3);
if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/ if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
@ -1333,6 +1340,9 @@ static bool construct(
dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f; dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f; dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f; dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
}
} }
if (!dc->public.debug.disable_pplib_clock_request) if (!dc->public.debug.disable_pplib_clock_request)

3
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View File

@ -115,6 +115,9 @@
#define RAVEN_UNKNOWN 0xFF #define RAVEN_UNKNOWN 0xFF
#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
#define RAVEN1_F0 0xF0
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
#define FAMILY_RV 142 /* DCN 1*/ #define FAMILY_RV 142 /* DCN 1*/