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drm/amd/display: update predefined latency for Rv1_F0
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1323,6 +1323,13 @@ static bool construct(
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dc->dcn_ip = dcn10_ip_defaults;
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dc->dcn_soc = dcn10_soc_defaults;
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if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
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dc->dcn_soc.urgent_latency = 3;
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dc->public.debug.disable_dmcu = true;
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dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
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}
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dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
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ASSERT(dc->dcn_soc.number_of_channels < 3);
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if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
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@ -1333,6 +1340,9 @@ static bool construct(
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dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
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dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
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dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
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if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
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dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
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}
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}
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if (!dc->public.debug.disable_pplib_clock_request)
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@ -115,6 +115,9 @@
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#define RAVEN_UNKNOWN 0xFF
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#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
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#define RAVEN1_F0 0xF0
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#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
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#define FAMILY_RV 142 /* DCN 1*/
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