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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 21:40:54 +07:00
pinctrl: sirf: switch driver to use gpiolib irqchip helpers
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
c5eb757ca8
commit
7420d2d09b
@ -289,6 +289,7 @@ config PINCTRL_SIRF
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bool "CSR SiRFprimaII/SiRFmarco pin controller driver"
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depends on ARCH_SIRF
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select PINMUX
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select GPIOLIB_IRQCHIP
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config PINCTRL_SUNXI
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bool
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@ -14,8 +14,6 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/consumer.h>
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@ -27,7 +25,6 @@
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <asm/mach/irq.h>
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#include "pinctrl-sirf.h"
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@ -41,7 +38,6 @@ struct sirfsoc_gpio_bank {
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struct sirfsoc_gpio_chip {
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struct of_mm_gpio_chip chip;
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struct irq_domain *domain;
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bool is_marco; /* for marco, some registers are different with prima2 */
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struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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};
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@ -450,15 +446,11 @@ static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
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return &sgpio_chip.sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
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}
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static int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return irq_create_mapping(sgpio_chip.domain, offset);
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}
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static inline int sirfsoc_gpio_to_bankoff(unsigned int gpio)
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{
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return gpio % SIRFSOC_GPIO_BANK_SIZE;
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}
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static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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@ -566,38 +558,28 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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return 0;
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}
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static int sirfsoc_gpio_irq_reqres(struct irq_data *d)
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{
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if (gpio_lock_as_irq(&sgpio_chip.chip.gc, d->hwirq)) {
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dev_err(sgpio_chip.chip.gc.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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d->hwirq);
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return -EINVAL;
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}
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return 0;
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}
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static void sirfsoc_gpio_irq_relres(struct irq_data *d)
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{
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gpio_unlock_as_irq(&sgpio_chip.chip.gc, d->hwirq);
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}
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static struct irq_chip sirfsoc_irq_chip = {
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.name = "sirf-gpio-irq",
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.irq_ack = sirfsoc_gpio_irq_ack,
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.irq_mask = sirfsoc_gpio_irq_mask,
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.irq_unmask = sirfsoc_gpio_irq_unmask,
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.irq_set_type = sirfsoc_gpio_irq_type,
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.irq_request_resources = sirfsoc_gpio_irq_reqres,
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.irq_release_resources = sirfsoc_gpio_irq_relres,
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};
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static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
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struct sirfsoc_gpio_bank *bank;
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u32 status, ctrl;
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int idx = 0;
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struct irq_chip *chip = irq_get_chip(irq);
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int i;
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for (i = 0; i < SIRFSOC_GPIO_BANK_SIZE; i++) {
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bank = &sgpio_chip.sgpio_bank[i];
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if (bank->parent_irq == irq)
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break;
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}
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BUG_ON (i == SIRFSOC_GPIO_BANK_SIZE);
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chained_irq_enter(chip, desc);
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@ -620,7 +602,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
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pr_debug("%s: gpio id %d idx %d happens\n",
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__func__, bank->id, idx);
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generic_handle_irq(irq_find_mapping(sgpio_chip.domain, idx +
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generic_handle_irq(irq_find_mapping(sgpio_chip.chip.gc.irqdomain, idx +
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bank->id * SIRFSOC_GPIO_BANK_SIZE));
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}
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@ -768,26 +750,6 @@ static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
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spin_unlock_irqrestore(&bank->lock, flags);
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}
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static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct sirfsoc_gpio_bank *bank = d->host_data;
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if (!bank)
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return -EINVAL;
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irq_set_chip(irq, &sirfsoc_irq_chip);
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irq_set_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
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.map = sirfsoc_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static void sirfsoc_gpio_set_pullup(const u32 *pullups)
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{
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int i, n;
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@ -826,7 +788,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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struct sirfsoc_gpio_bank *bank;
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void __iomem *regs;
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struct platform_device *pdev;
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struct irq_domain *domain;
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bool is_marco = false;
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u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
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@ -842,21 +803,12 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
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is_marco = 1;
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domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
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&sirfsoc_gpio_irq_simple_ops, &sgpio_chip);
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if (!domain) {
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pr_err("%s: Failed to create irqdomain\n", np->full_name);
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err = -ENOSYS;
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goto out;
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}
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sgpio_chip.chip.gc.request = sirfsoc_gpio_request;
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sgpio_chip.chip.gc.free = sirfsoc_gpio_free;
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sgpio_chip.chip.gc.direction_input = sirfsoc_gpio_direction_input;
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sgpio_chip.chip.gc.get = sirfsoc_gpio_get_value;
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sgpio_chip.chip.gc.direction_output = sirfsoc_gpio_direction_output;
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sgpio_chip.chip.gc.set = sirfsoc_gpio_set_value;
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sgpio_chip.chip.gc.to_irq = sirfsoc_gpio_to_irq;
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sgpio_chip.chip.gc.base = 0;
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sgpio_chip.chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
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sgpio_chip.chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
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@ -866,15 +818,24 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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sgpio_chip.chip.gc.dev = &pdev->dev;
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sgpio_chip.chip.regs = regs;
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sgpio_chip.is_marco = is_marco;
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sgpio_chip.domain = domain;
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err = gpiochip_add(&sgpio_chip.chip.gc);
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if (err) {
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pr_err("%s: error in probe function with status %d\n",
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dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
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np->full_name, err);
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goto out;
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}
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err = gpiochip_irqchip_add(&sgpio_chip.chip.gc,
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&sirfsoc_irq_chip,
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0, handle_level_irq,
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IRQ_TYPE_NONE);
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if (err) {
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dev_err(&pdev->dev,
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"could not connect irqchip to gpiochip\n");
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goto out;
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}
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for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
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bank = &sgpio_chip.sgpio_bank[i];
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spin_lock_init(&bank->lock);
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@ -884,8 +845,10 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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goto out;
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}
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irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
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irq_set_handler_data(bank->parent_irq, bank);
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gpiochip_set_chained_irqchip(&sgpio_chip.chip.gc,
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&sirfsoc_irq_chip,
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bank->parent_irq,
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sirfsoc_gpio_handle_irq);
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}
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if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
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