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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iwlwifi: move ucode alive related code to separate file
uCode alive for iwlagn based devices share the same functions. Move those functions from iwl-5000.c to iwl-agn-ucode.c. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
This commit is contained in:
Wey-Yi Guy
Reinette Chatre
parent
19e6cda094
commit
741a626627
@ -178,8 +178,8 @@ static struct iwl_lib_ops iwl1000_lib = {
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.dump_nic_error_log = iwl_dump_nic_error_log,
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.dump_csr = iwl_dump_csr,
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.dump_fh = iwl_dump_fh,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.init_alive_start = iwlagn_init_alive_start,
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.alive_notify = iwlagn_alive_notify,
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.send_tx_power = iwl5000_send_tx_power,
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.update_chain_flags = iwl_update_chain_flags,
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.apm_ops = {
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@ -65,19 +65,6 @@
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#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
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#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
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static const s8 iwl5000_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWLAGN_CMD_FIFO_NUM,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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};
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/* NIC configuration for 5000 series */
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void iwl5000_nic_config(struct iwl_priv *priv)
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{
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@ -240,220 +227,6 @@ static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
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priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
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}
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/*
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* Calibration
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*/
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static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
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{
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struct iwl_calib_xtal_freq_cmd cmd;
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__le16 *xtal_calib =
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(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
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cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
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return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
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(u8 *)&cmd, sizeof(cmd));
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}
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static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
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{
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struct iwl_calib_cfg_cmd calib_cfg_cmd;
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struct iwl_host_cmd cmd = {
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.id = CALIBRATION_CFG_CMD,
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.len = sizeof(struct iwl_calib_cfg_cmd),
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.data = &calib_cfg_cmd,
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};
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memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
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calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
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return iwl_send_cmd(priv, &cmd);
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}
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static void iwl5000_rx_calib_result(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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{
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struct iwl_rx_packet *pkt = rxb_addr(rxb);
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struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
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int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
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int index;
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/* reduce the size of the length field itself */
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len -= 4;
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/* Define the order in which the results will be sent to the runtime
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* uCode. iwl_send_calib_results sends them in a row according to their
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* index. We sort them here */
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switch (hdr->op_code) {
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case IWL_PHY_CALIBRATE_DC_CMD:
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index = IWL_CALIB_DC;
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break;
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case IWL_PHY_CALIBRATE_LO_CMD:
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index = IWL_CALIB_LO;
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break;
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case IWL_PHY_CALIBRATE_TX_IQ_CMD:
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index = IWL_CALIB_TX_IQ;
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break;
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case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
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index = IWL_CALIB_TX_IQ_PERD;
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break;
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case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
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index = IWL_CALIB_BASE_BAND;
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break;
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default:
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IWL_ERR(priv, "Unknown calibration notification %d\n",
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hdr->op_code);
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return;
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}
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iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
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}
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static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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{
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IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
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queue_work(priv->workqueue, &priv->restart);
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}
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void iwl5000_init_alive_start(struct iwl_priv *priv)
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{
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int ret = 0;
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/* Check alive response for "valid" sign from uCode */
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if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
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/* We had an error bringing up the hardware, so take it
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* all the way back down so we can try again */
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IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
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goto restart;
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}
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/* initialize uCode was loaded... verify inst image.
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* This is a paranoid check, because we would not have gotten the
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* "initialize" alive if code weren't properly loaded. */
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if (iwl_verify_ucode(priv)) {
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/* Runtime instruction load was bad;
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* take it all the way back down so we can try again */
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IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
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goto restart;
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}
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ret = priv->cfg->ops->lib->alive_notify(priv);
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if (ret) {
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IWL_WARN(priv,
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"Could not complete ALIVE transition: %d\n", ret);
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goto restart;
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}
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iwl5000_send_calib_cfg(priv);
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return;
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restart:
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/* real restart (first load init_ucode) */
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queue_work(priv->workqueue, &priv->restart);
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}
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int iwl5000_alive_notify(struct iwl_priv *priv)
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{
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u32 a;
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unsigned long flags;
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int i, chan;
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u32 reg_val;
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spin_lock_irqsave(&priv->lock, flags);
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priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
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for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
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a += 4)
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr +
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IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
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iwl_write_targ_mem(priv, a, 0);
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iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
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priv->scd_bc_tbls.dma >> 10);
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/* Enable DMA channel */
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for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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/* Update FH chicken bits */
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reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
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iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
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IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
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iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
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/* initiate the queues */
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for (i = 0; i < priv->hw_params.max_txq_num; i++) {
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iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
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sizeof(u32),
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((SCD_WIN_SIZE <<
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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((SCD_FRAME_LIMIT <<
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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}
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iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
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IWL_MASK(0, priv->hw_params.max_txq_num));
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/* Activate all Tx DMA/FIFO channels */
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priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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/* make sure all queue are not stopped */
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memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
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for (i = 0; i < 4; i++)
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atomic_set(&priv->queue_stop_count[i], 0);
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/* reset to 0 to enable all the queue first */
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priv->txq_ctx_active_msk = 0;
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/* map qos queues to fifos one-to-one */
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BUILD_BUG_ON(ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo) != 10);
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for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
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int ac = iwl5000_default_queue_to_tx_fifo[i];
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iwl_txq_ctx_activate(priv, i);
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if (ac == IWL_TX_FIFO_UNUSED)
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continue;
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iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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iwl_send_wimax_coex(priv);
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iwl5000_set_Xtal_calib(priv);
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iwl_send_calib_results(priv);
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return 0;
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}
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int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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{
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if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
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@ -733,9 +506,9 @@ void iwl5000_rx_handler_setup(struct iwl_priv *priv)
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{
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/* init calibration handlers */
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priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
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iwl5000_rx_calib_result;
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iwlagn_rx_calib_result;
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priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
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iwl5000_rx_calib_complete;
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iwlagn_rx_calib_complete;
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priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
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}
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@ -851,8 +624,8 @@ struct iwl_lib_ops iwl5000_lib = {
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.dump_csr = iwl_dump_csr,
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.dump_fh = iwl_dump_fh,
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.load_ucode = iwlagn_load_ucode,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.init_alive_start = iwlagn_init_alive_start,
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.alive_notify = iwlagn_alive_notify,
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.send_tx_power = iwl5000_send_tx_power,
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.update_chain_flags = iwl_update_chain_flags,
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.set_channel_switch = iwl5000_hw_channel_switch,
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@ -908,8 +681,8 @@ static struct iwl_lib_ops iwl5150_lib = {
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.dump_nic_error_log = iwl_dump_nic_error_log,
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.dump_csr = iwl_dump_csr,
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.load_ucode = iwlagn_load_ucode,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.init_alive_start = iwlagn_init_alive_start,
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.alive_notify = iwlagn_alive_notify,
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.send_tx_power = iwl5000_send_tx_power,
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.update_chain_flags = iwl_update_chain_flags,
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.set_channel_switch = iwl5000_hw_channel_switch,
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@ -242,8 +242,8 @@ static struct iwl_lib_ops iwl6000_lib = {
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.dump_nic_error_log = iwl_dump_nic_error_log,
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.dump_csr = iwl_dump_csr,
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.dump_fh = iwl_dump_fh,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.init_alive_start = iwlagn_init_alive_start,
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.alive_notify = iwlagn_alive_notify,
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.send_tx_power = iwl5000_send_tx_power,
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.update_chain_flags = iwl_update_chain_flags,
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.set_channel_switch = iwl6000_hw_channel_switch,
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@ -309,8 +309,8 @@ static struct iwl_lib_ops iwl6050_lib = {
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.dump_nic_error_log = iwl_dump_nic_error_log,
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.dump_csr = iwl_dump_csr,
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.dump_fh = iwl_dump_fh,
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.init_alive_start = iwl5000_init_alive_start,
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.alive_notify = iwl5000_alive_notify,
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.init_alive_start = iwlagn_init_alive_start,
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.alive_notify = iwlagn_alive_notify,
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.send_tx_power = iwl5000_send_tx_power,
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.update_chain_flags = iwl_update_chain_flags,
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.set_channel_switch = iwl6000_hw_channel_switch,
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@ -35,7 +35,22 @@
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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#include "iwl-agn-hw.h"
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#include "iwl-agn.h"
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static const s8 iwlagn_default_queue_to_tx_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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IWLAGN_CMD_FIFO_NUM,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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IWL_TX_FIFO_UNUSED,
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};
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/*
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* ucode
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@ -184,3 +199,218 @@ struct iwl_ucode_ops iwlagn_ucode = {
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.get_boot_size = iwlagn_ucode_get_boot_size,
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.get_data = iwlagn_ucode_get_data,
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};
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/*
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* Calibration
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*/
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static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
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{
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struct iwl_calib_xtal_freq_cmd cmd;
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__le16 *xtal_calib =
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(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
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cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
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cmd.hdr.first_group = 0;
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cmd.hdr.groups_num = 1;
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cmd.hdr.data_valid = 1;
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cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
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cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
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return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
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(u8 *)&cmd, sizeof(cmd));
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}
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static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
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{
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struct iwl_calib_cfg_cmd calib_cfg_cmd;
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struct iwl_host_cmd cmd = {
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.id = CALIBRATION_CFG_CMD,
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.len = sizeof(struct iwl_calib_cfg_cmd),
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.data = &calib_cfg_cmd,
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};
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memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
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calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
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calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
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return iwl_send_cmd(priv, &cmd);
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}
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void iwlagn_rx_calib_result(struct iwl_priv *priv,
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struct iwl_rx_mem_buffer *rxb)
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{
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struct iwl_rx_packet *pkt = rxb_addr(rxb);
|
||||
struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
|
||||
int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
|
||||
int index;
|
||||
|
||||
/* reduce the size of the length field itself */
|
||||
len -= 4;
|
||||
|
||||
/* Define the order in which the results will be sent to the runtime
|
||||
* uCode. iwl_send_calib_results sends them in a row according to
|
||||
* their index. We sort them here
|
||||
*/
|
||||
switch (hdr->op_code) {
|
||||
case IWL_PHY_CALIBRATE_DC_CMD:
|
||||
index = IWL_CALIB_DC;
|
||||
break;
|
||||
case IWL_PHY_CALIBRATE_LO_CMD:
|
||||
index = IWL_CALIB_LO;
|
||||
break;
|
||||
case IWL_PHY_CALIBRATE_TX_IQ_CMD:
|
||||
index = IWL_CALIB_TX_IQ;
|
||||
break;
|
||||
case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
|
||||
index = IWL_CALIB_TX_IQ_PERD;
|
||||
break;
|
||||
case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
|
||||
index = IWL_CALIB_BASE_BAND;
|
||||
break;
|
||||
default:
|
||||
IWL_ERR(priv, "Unknown calibration notification %d\n",
|
||||
hdr->op_code);
|
||||
return;
|
||||
}
|
||||
iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
|
||||
}
|
||||
|
||||
void iwlagn_rx_calib_complete(struct iwl_priv *priv,
|
||||
struct iwl_rx_mem_buffer *rxb)
|
||||
{
|
||||
IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
|
||||
queue_work(priv->workqueue, &priv->restart);
|
||||
}
|
||||
|
||||
void iwlagn_init_alive_start(struct iwl_priv *priv)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* Check alive response for "valid" sign from uCode */
|
||||
if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
|
||||
/* We had an error bringing up the hardware, so take it
|
||||
* all the way back down so we can try again */
|
||||
IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
|
||||
goto restart;
|
||||
}
|
||||
|
||||
/* initialize uCode was loaded... verify inst image.
|
||||
* This is a paranoid check, because we would not have gotten the
|
||||
* "initialize" alive if code weren't properly loaded. */
|
||||
if (iwl_verify_ucode(priv)) {
|
||||
/* Runtime instruction load was bad;
|
||||
* take it all the way back down so we can try again */
|
||||
IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
|
||||
goto restart;
|
||||
}
|
||||
|
||||
ret = priv->cfg->ops->lib->alive_notify(priv);
|
||||
if (ret) {
|
||||
IWL_WARN(priv,
|
||||
"Could not complete ALIVE transition: %d\n", ret);
|
||||
goto restart;
|
||||
}
|
||||
|
||||
iwlagn_send_calib_cfg(priv);
|
||||
return;
|
||||
|
||||
restart:
|
||||
/* real restart (first load init_ucode) */
|
||||
queue_work(priv->workqueue, &priv->restart);
|
||||
}
|
||||
|
||||
int iwlagn_alive_notify(struct iwl_priv *priv)
|
||||
{
|
||||
u32 a;
|
||||
unsigned long flags;
|
||||
int i, chan;
|
||||
u32 reg_val;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
|
||||
a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
|
||||
for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
|
||||
a += 4)
|
||||
iwl_write_targ_mem(priv, a, 0);
|
||||
for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
|
||||
a += 4)
|
||||
iwl_write_targ_mem(priv, a, 0);
|
||||
for (; a < priv->scd_base_addr +
|
||||
IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
|
||||
iwl_write_targ_mem(priv, a, 0);
|
||||
|
||||
iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
|
||||
priv->scd_bc_tbls.dma >> 10);
|
||||
|
||||
/* Enable DMA channel */
|
||||
for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
|
||||
iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
|
||||
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
|
||||
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
|
||||
|
||||
/* Update FH chicken bits */
|
||||
reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
|
||||
iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
|
||||
reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
|
||||
|
||||
iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
|
||||
IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
|
||||
iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
|
||||
|
||||
/* initiate the queues */
|
||||
for (i = 0; i < priv->hw_params.max_txq_num; i++) {
|
||||
iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
|
||||
iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
|
||||
iwl_write_targ_mem(priv, priv->scd_base_addr +
|
||||
IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
|
||||
iwl_write_targ_mem(priv, priv->scd_base_addr +
|
||||
IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
|
||||
sizeof(u32),
|
||||
((SCD_WIN_SIZE <<
|
||||
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
|
||||
IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
|
||||
((SCD_FRAME_LIMIT <<
|
||||
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
|
||||
IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
|
||||
}
|
||||
|
||||
iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
|
||||
IWL_MASK(0, priv->hw_params.max_txq_num));
|
||||
|
||||
/* Activate all Tx DMA/FIFO channels */
|
||||
priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
|
||||
|
||||
iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
|
||||
|
||||
/* make sure all queue are not stopped */
|
||||
memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
|
||||
for (i = 0; i < 4; i++)
|
||||
atomic_set(&priv->queue_stop_count[i], 0);
|
||||
|
||||
/* reset to 0 to enable all the queue first */
|
||||
priv->txq_ctx_active_msk = 0;
|
||||
/* map qos queues to fifos one-to-one */
|
||||
BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo); i++) {
|
||||
int ac = iwlagn_default_queue_to_tx_fifo[i];
|
||||
|
||||
iwl_txq_ctx_activate(priv, i);
|
||||
|
||||
if (ac == IWL_TX_FIFO_UNUSED)
|
||||
continue;
|
||||
|
||||
iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
iwl_send_wimax_coex(priv);
|
||||
|
||||
iwlagn_set_Xtal_calib(priv);
|
||||
iwl_send_calib_results(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -77,9 +77,6 @@ irqreturn_t iwl_isr_ict(int irq, void *data);
|
||||
bool iwl_good_ack_health(struct iwl_priv *priv,
|
||||
struct iwl_rx_packet *pkt);
|
||||
|
||||
/* uCode */
|
||||
int iwlagn_load_ucode(struct iwl_priv *priv);
|
||||
|
||||
/* tx queue */
|
||||
void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
|
||||
int txq_id, u32 index);
|
||||
@ -97,4 +94,13 @@ int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
|
||||
u16 ssn_idx, u8 tx_fifo);
|
||||
void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask);
|
||||
|
||||
/* uCode */
|
||||
int iwlagn_load_ucode(struct iwl_priv *priv);
|
||||
void iwlagn_rx_calib_result(struct iwl_priv *priv,
|
||||
struct iwl_rx_mem_buffer *rxb);
|
||||
void iwlagn_rx_calib_complete(struct iwl_priv *priv,
|
||||
struct iwl_rx_mem_buffer *rxb);
|
||||
void iwlagn_init_alive_start(struct iwl_priv *priv);
|
||||
int iwlagn_alive_notify(struct iwl_priv *priv);
|
||||
|
||||
#endif /* __iwl_agn_h__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user