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ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

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mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2016-01-21 13:26:38 +08:00 committed by Maxime Ripard
parent db30fce1ee
commit 74124439b9
1 changed files with 3 additions and 0 deletions
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arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
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@ -109,10 +109,13 @@ &mmc2 {
vmmc-supply = <&reg_vcc3v0>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
/* eMMC is missing pull-ups */
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};