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drm/i915: Drop posting reads to flush master interrupts
We do not need to do a posting read of our uncached mmio write to re-enable the master interrupt lines after handling an interrupt, so don't. This saves us a slow UC read before we can process the interrupt, most noticeable in execlists where any stalls imposes extra latency on GPU command execution. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-1-chris@chris-wilson.co.uk
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@ -2183,7 +2183,6 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
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I915_WRITE(VLV_IER, ier);
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I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
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POSTING_READ(VLV_MASTER_IER);
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if (gt_iir)
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snb_gt_irq_handler(dev_priv, gt_iir);
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@ -2268,7 +2267,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
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I915_WRITE(VLV_IER, ier);
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I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
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POSTING_READ(GEN8_MASTER_IRQ);
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gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
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@ -2637,7 +2635,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
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/* disable master interrupt before clearing iir */
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de_ier = I915_READ(DEIER);
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I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
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POSTING_READ(DEIER);
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/* Disable south interrupts. We'll only write to SDEIIR once, so further
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* interrupts will will be stored on its back queue, and then we'll be
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@ -2647,7 +2644,6 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
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if (!HAS_PCH_NOP(dev_priv)) {
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sde_ier = I915_READ(SDEIER);
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I915_WRITE(SDEIER, 0);
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POSTING_READ(SDEIER);
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}
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/* Find, clear, then process each source of interrupt */
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@ -2682,11 +2678,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
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}
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I915_WRITE(DEIER, de_ier);
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POSTING_READ(DEIER);
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if (!HAS_PCH_NOP(dev_priv)) {
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if (!HAS_PCH_NOP(dev_priv))
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I915_WRITE(SDEIER, sde_ier);
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POSTING_READ(SDEIER);
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}
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/* IRQs are synced during runtime_suspend, we don't require a wakeref */
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enable_rpm_wakeref_asserts(dev_priv);
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