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drm/panfrost: Consolidate reset handling
Runtime PM resume and job timeouts both call the same sequence of functions, so consolidate them to a common function. This will make changing the reset related code easier. The MMU also needs some re-initialization on reset, so rework its call. In the process, we hide the address space details within the MMU code in preparation to support multiple address spaces. Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190808222200.13176-7-robh@kernel.org
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@ -254,18 +254,22 @@ const char *panfrost_exception_name(struct panfrost_device *pfdev, u32 exception
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return "UNKNOWN";
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}
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void panfrost_device_reset(struct panfrost_device *pfdev)
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{
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panfrost_gpu_soft_reset(pfdev);
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panfrost_gpu_power_on(pfdev);
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panfrost_mmu_reset(pfdev);
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panfrost_job_enable_interrupts(pfdev);
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}
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#ifdef CONFIG_PM
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int panfrost_device_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct panfrost_device *pfdev = platform_get_drvdata(pdev);
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panfrost_gpu_soft_reset(pfdev);
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/* TODO: Re-enable all other address spaces */
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panfrost_gpu_power_on(pfdev);
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panfrost_mmu_enable(pfdev, 0);
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panfrost_job_enable_interrupts(pfdev);
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panfrost_device_reset(pfdev);
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panfrost_devfreq_resume(pfdev);
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return 0;
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@ -132,6 +132,7 @@ int panfrost_unstable_ioctl_check(void);
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int panfrost_device_init(struct panfrost_device *pfdev);
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void panfrost_device_fini(struct panfrost_device *pfdev);
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void panfrost_device_reset(struct panfrost_device *pfdev);
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int panfrost_device_resume(struct device *dev);
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int panfrost_device_suspend(struct device *dev);
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@ -395,12 +395,7 @@ static void panfrost_job_timedout(struct drm_sched_job *sched_job)
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/* panfrost_core_dump(pfdev); */
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panfrost_devfreq_record_transition(pfdev, js);
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panfrost_gpu_soft_reset(pfdev);
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/* TODO: Re-enable all other address spaces */
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panfrost_mmu_enable(pfdev, 0);
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panfrost_gpu_power_on(pfdev);
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panfrost_job_enable_interrupts(pfdev);
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panfrost_device_reset(pfdev);
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for (i = 0; i < NUM_JOB_SLOTS; i++)
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drm_sched_resubmit_jobs(&pfdev->js->queue[i].sched);
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@ -105,15 +105,12 @@ static int mmu_hw_do_operation(struct panfrost_device *pfdev, u32 as_nr,
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return ret;
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}
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void panfrost_mmu_enable(struct panfrost_device *pfdev, u32 as_nr)
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static void panfrost_mmu_enable(struct panfrost_device *pfdev, u32 as_nr)
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{
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struct io_pgtable_cfg *cfg = &pfdev->mmu->pgtbl_cfg;
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u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
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u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
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mmu_write(pfdev, MMU_INT_CLEAR, ~0);
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mmu_write(pfdev, MMU_INT_MASK, ~0);
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mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
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mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), transtab >> 32);
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@ -137,6 +134,14 @@ static void mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
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write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
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}
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void panfrost_mmu_reset(struct panfrost_device *pfdev)
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{
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panfrost_mmu_enable(pfdev, 0);
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mmu_write(pfdev, MMU_INT_CLEAR, ~0);
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mmu_write(pfdev, MMU_INT_MASK, ~0);
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}
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static size_t get_pgsize(u64 addr, size_t size)
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{
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if (addr & (SZ_2M - 1) || size < SZ_2M)
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@ -375,9 +380,6 @@ int panfrost_mmu_init(struct panfrost_device *pfdev)
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dev_err(pfdev->dev, "failed to request mmu irq");
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return err;
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}
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mmu_write(pfdev, MMU_INT_CLEAR, ~0);
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mmu_write(pfdev, MMU_INT_MASK, ~0);
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pfdev->mmu->pgtbl_cfg = (struct io_pgtable_cfg) {
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.pgsize_bitmap = SZ_4K | SZ_2M,
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.ias = FIELD_GET(0xff, pfdev->features.mmu_features),
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@ -11,7 +11,6 @@ void panfrost_mmu_unmap(struct panfrost_gem_object *bo);
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int panfrost_mmu_init(struct panfrost_device *pfdev);
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void panfrost_mmu_fini(struct panfrost_device *pfdev);
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void panfrost_mmu_enable(struct panfrost_device *pfdev, u32 as_nr);
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void panfrost_mmu_reset(struct panfrost_device *pfdev);
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#endif
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