AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-30 08:46:43 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

Browse Source 
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
on bits in both the System Control Unit and the LPC Host Controller.

The Aspeed LPC Host Controller is described as a child node of the
LPC host-range syscon device for arbitration of access by the host
controller and pinmux drivers.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Andrew Jeffery 2016-12-20 17:45:34 +10:30 committed by Lee Jones
parent 28fe081612
commit 73bee1d330
1 changed files with 26 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
View File

@ -109,3 +109,29 @@ lpc: lpc@1e789000 {
};
};
Host Node Children
==================
LPC Host Controller
-------------------
The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
between the host and the baseboard management controller. The registers exist
in the "host" portion of the Aspeed LPC controller, which must be the parent of
the LPC host controller node.
Required properties:
- compatible: One of:
"aspeed,ast2400-lhc";
"aspeed,ast2500-lhc";
- reg: contains offset/length values of the LHC memory regions. In the
AST2400 and AST2500 there are two regions.
Example:
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};