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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iommu/vt-d: Setup context and enable RID2PASID support
This patch enables the translation for requests without PASID in the scalable mode by setting up the root and context entries. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Lu Baolu
Joerg Roedel
parent
ca6e322d60
commit
7373a8cc38
@ -1197,6 +1197,8 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
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unsigned long flag;
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addr = virt_to_phys(iommu->root_entry);
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if (sm_supported(iommu))
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addr |= DMA_RTADDR_SMT;
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
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@ -1918,6 +1920,56 @@ static void domain_exit(struct dmar_domain *domain)
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free_domain_mem(domain);
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}
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/*
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* Get the PASID directory size for scalable mode context entry.
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* Value of X in the PDTS field of a scalable mode context entry
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* indicates PASID directory with 2^(X + 7) entries.
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*/
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static inline unsigned long context_get_sm_pds(struct pasid_table *table)
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{
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int pds, max_pde;
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max_pde = table->max_pasid >> PASID_PDE_SHIFT;
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pds = find_first_bit((unsigned long *)&max_pde, MAX_NR_PASID_BITS);
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if (pds < 7)
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return 0;
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return pds - 7;
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}
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/*
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* Set the RID_PASID field of a scalable mode context entry. The
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* IOMMU hardware will use the PASID value set in this field for
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* DMA translations of DMA requests without PASID.
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*/
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static inline void
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context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid)
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{
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context->hi |= pasid & ((1 << 20) - 1);
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context->hi |= (1 << 20);
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}
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/*
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* Set the DTE(Device-TLB Enable) field of a scalable mode context
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* entry.
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*/
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static inline void context_set_sm_dte(struct context_entry *context)
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{
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context->lo |= (1 << 2);
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}
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/*
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* Set the PRE(Page Request Enable) field of a scalable mode context
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* entry.
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*/
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static inline void context_set_sm_pre(struct context_entry *context)
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{
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context->lo |= (1 << 4);
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}
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/* Convert value to context PASID directory size field coding. */
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#define context_pdts(pds) (((pds) & 0x7) << 9)
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static int domain_context_mapping_one(struct dmar_domain *domain,
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struct intel_iommu *iommu,
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struct pasid_table *table,
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@ -1928,8 +1980,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
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struct device_domain_info *info = NULL;
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struct context_entry *context;
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unsigned long flags;
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struct dma_pte *pgd;
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int ret, agaw;
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int ret;
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WARN_ON(did == 0);
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@ -1975,41 +2026,67 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
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}
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}
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pgd = domain->pgd;
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context_clear_entry(context);
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context_set_domain_id(context, did);
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/*
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* Skip top levels of page tables for iommu which has less agaw
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* than default. Unnecessary for PT mode.
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*/
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if (translation != CONTEXT_TT_PASS_THROUGH) {
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for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
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ret = -ENOMEM;
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pgd = phys_to_virt(dma_pte_addr(pgd));
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if (!dma_pte_present(pgd))
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goto out_unlock;
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}
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if (sm_supported(iommu)) {
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unsigned long pds;
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WARN_ON(!table);
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/* Setup the PASID DIR pointer: */
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pds = context_get_sm_pds(table);
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context->lo = (u64)virt_to_phys(table->table) |
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context_pdts(pds);
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/* Setup the RID_PASID field: */
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context_set_sm_rid2pasid(context, PASID_RID2PASID);
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/*
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* Setup the Device-TLB enable bit and Page request
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* Enable bit:
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*/
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info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
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if (info && info->ats_supported)
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translation = CONTEXT_TT_DEV_IOTLB;
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else
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translation = CONTEXT_TT_MULTI_LEVEL;
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context_set_address_root(context, virt_to_phys(pgd));
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context_set_address_width(context, agaw);
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context_set_sm_dte(context);
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if (info && info->pri_supported)
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context_set_sm_pre(context);
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} else {
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/*
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* In pass through mode, AW must be programmed to
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* indicate the largest AGAW value supported by
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* hardware. And ASR is ignored by hardware.
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*/
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context_set_address_width(context, iommu->msagaw);
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struct dma_pte *pgd = domain->pgd;
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int agaw;
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context_set_domain_id(context, did);
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context_set_translation_type(context, translation);
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if (translation != CONTEXT_TT_PASS_THROUGH) {
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/*
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* Skip top levels of page tables for iommu which has
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* less agaw than default. Unnecessary for PT mode.
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*/
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for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
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ret = -ENOMEM;
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pgd = phys_to_virt(dma_pte_addr(pgd));
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if (!dma_pte_present(pgd))
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goto out_unlock;
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}
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info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
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if (info && info->ats_supported)
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translation = CONTEXT_TT_DEV_IOTLB;
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else
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translation = CONTEXT_TT_MULTI_LEVEL;
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context_set_address_root(context, virt_to_phys(pgd));
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context_set_address_width(context, agaw);
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} else {
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/*
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* In pass through mode, AW must be programmed to
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* indicate the largest AGAW value supported by
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* hardware. And ASR is ignored by hardware.
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*/
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context_set_address_width(context, iommu->msagaw);
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}
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}
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context_set_translation_type(context, translation);
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context_set_fault_enable(context);
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context_set_present(context);
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domain_flush_cache(domain, context, sizeof(*context));
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@ -5180,7 +5257,6 @@ static void intel_iommu_put_resv_regions(struct device *dev,
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}
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#ifdef CONFIG_INTEL_IOMMU_SVM
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#define MAX_NR_PASID_BITS (20)
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static inline unsigned long intel_iommu_get_pts(struct device *dev)
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{
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int pts, max_pasid;
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@ -17,6 +17,7 @@
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#define PASID_PTE_PRESENT 1
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#define PDE_PFN_MASK PAGE_MASK
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#define PASID_PDE_SHIFT 6
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#define MAX_NR_PASID_BITS 20
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/*
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* Domain ID reserved for pasid entries programmed for first-level
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@ -258,6 +258,7 @@
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/* DMA_RTADDR_REG */
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#define DMA_RTADDR_RTT (((u64)1) << 11)
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#define DMA_RTADDR_SMT (((u64)1) << 10)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (((u64)1) << 63)
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