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net: atlantic: QoS implementation: max_rate

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This patch adds initial support for mqprio rate limiters (max_rate only).

Atlantic HW supports Rate-Shaping for time-sensitive traffic at per
Traffic Class (TC) granularity.
Target rate is defined by:
* nominal link rate (always 10G);
* rate factor (ratio between nominal rate and max allowed).

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mark Starovoytov 2020-05-22 11:19:43 +03:00 committed by David S. Miller
parent b9e989262a
commit 7327699f35
10 changed files with 235 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/aquantia/atlantic/aq_hw.h
View File

@ -35,6 +35,9 @@ enum aq_tc_mode {
(AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
#define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU
/* Used for rate to Mbps conversion */
#define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */
/* NIC H/W capabilities */
struct aq_hw_caps_s {
u64 hw_features;

30
drivers/net/ethernet/aquantia/atlantic/aq_main.c
View File

@ -333,8 +333,12 @@ static int aq_ndo_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto,
}
static int aq_validate_mqprio_opt(struct aq_nic_s *self,
struct tc_mqprio_qopt_offload *mqprio,
const unsigned int num_tc)
{
const bool has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE);
int i;
if (num_tc > aq_hw_num_tcs(self->aq_hw)) {
netdev_err(self->ndev, "Too many TCs requested\n");
return -EOPNOTSUPP;
@ -345,25 +349,43 @@ static int aq_validate_mqprio_opt(struct aq_nic_s *self,
return -EOPNOTSUPP;
}
for (i = 0; i < num_tc; i++) {
if (has_min_rate && mqprio->min_rate[i]) {
netdev_err(self->ndev,
"Min tx rate is not supported\n");
return -EOPNOTSUPP;
}
}
return 0;
}
static int aq_ndo_setup_tc(struct net_device *dev, enum tc_setup_type type,
void *type_data)
{
struct tc_mqprio_qopt_offload *mqprio = type_data;
struct aq_nic_s *aq_nic = netdev_priv(dev);
struct tc_mqprio_qopt *mqprio = type_data;
int err;
int i;
if (type != TC_SETUP_QDISC_MQPRIO)
return -EOPNOTSUPP;
err = aq_validate_mqprio_opt(aq_nic, mqprio->num_tc);
err = aq_validate_mqprio_opt(aq_nic, mqprio, mqprio->qopt.num_tc);
if (err)
return err;
return aq_nic_setup_tc_mqprio(aq_nic, mqprio->num_tc,
mqprio->prio_tc_map);
if (mqprio->flags & TC_MQPRIO_F_MAX_RATE) {
for (i = 0; i < mqprio->qopt.num_tc; i++) {
u64 max_rate = mqprio->max_rate[i];
do_div(max_rate, AQ_MBPS_DIVISOR);
aq_nic_setup_tc_max_rate(aq_nic, i, (u32)max_rate);
}
}
return aq_nic_setup_tc_mqprio(aq_nic, mqprio->qopt.num_tc,
mqprio->qopt.prio_tc_map);
}
static const struct net_device_ops aq_ndev_ops = {

20
drivers/net/ethernet/aquantia/atlantic/aq_nic.c
View File

@ -1324,3 +1324,23 @@ int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map)
return err;
}
int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
const u32 max_rate)
{
struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
if (tc >= AQ_CFG_TCS_MAX)
return -EINVAL;
if (max_rate && max_rate < 10) {
netdev_warn(self->ndev,
"Setting %s to the minimum usable value of %dMbps.\n",
"max rate", 10);
cfg->tc_max_rate[tc] = 10;
} else {
cfg->tc_max_rate[tc] = max_rate;
}
return 0;
}

3
drivers/net/ethernet/aquantia/atlantic/aq_nic.h
View File

@ -65,6 +65,7 @@ struct aq_nic_cfg_s {
u32 priv_flags;
u8 tcs;
u8 prio_tc_map[8];
u32 tc_max_rate[AQ_CFG_TCS_MAX];
struct aq_rss_parameters aq_rss;
u32 eee_speeds;
};
@ -194,4 +195,6 @@ u8 aq_nic_reserve_filter(struct aq_nic_s *self, enum aq_rx_filter_type type);
void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type,
u32 location);
int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map);
int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
const u32 max_rate);
#endif /* AQ_NIC_H */

58
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
View File

@ -138,6 +138,8 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
unsigned int prio = 0U;
u32 tc = 0U;
hw_atl_b0_hw_init_tx_tc_rate_limit(self);
if (cfg->is_ptp) {
tx_buff_size -= HW_ATL_B0_PTP_TXBUF_SIZE;
rx_buff_size -= HW_ATL_B0_PTP_RXBUF_SIZE;
@ -151,7 +153,6 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
/* TPS TC credits init */
hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
tx_buff_size /= cfg->tcs;
@ -162,8 +163,6 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
/* TX Packet Scheduler Data TC0 */
hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, tc);
hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, tc);
hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, tc);
hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, tc);
/* Tx buf size TC0 */
hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
@ -320,10 +319,61 @@ int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
return aq_hw_err_from_flags(self);
}
int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
{
/* Scale factor is based on the number of bits in fractional portion */
static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);
static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>
HW_ATL_TPS_DESC_RATE_Y_SHIFT;
struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
int tc;
hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);
for (tc = 0; tc != nic_cfg->tcs; tc++) {
const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;
const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, tc);
hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, tc);
hw_atl_tps_tx_desc_rate_en_set(self, desc, en);
if (en) {
/* Nominal rate is always 10G */
const u32 rate = 10000U * scale /
nic_cfg->tc_max_rate[tc];
const u32 rate_int = rate >>
HW_ATL_TPS_DESC_RATE_Y_WIDTH;
const u32 rate_frac = rate & frac_msk;
hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);
hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);
} else {
/* A value of 1 indicates the queue is not
* rate controlled.
*/
hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
}
}
for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {
const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);
hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
}
return aq_hw_err_from_flags(self);
}
static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
{
struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
/* Tx TC/Queue number config */
hw_atl_tpb_tps_tx_tc_mode_set(self, self->aq_nic_cfg->tc_mode);
hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode);
hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);

2
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
View File

@ -62,6 +62,8 @@ int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr);
int hw_atl_b0_hw_start(struct aq_hw_s *self);
int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self);
int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask);
int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask);
int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask);

36
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
View File

@ -1511,6 +1511,42 @@ void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
tx_pkt_shed_tc_data_weight);
}
void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw,
const u32 rate_mode)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_TX_DESC_RATE_MODE_ADR,
HW_ATL_TPS_TX_DESC_RATE_MODE_MSK,
HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT,
rate_mode);
}
void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 enable)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_EN_ADR(desc),
HW_ATL_TPS_DESC_RATE_EN_MSK,
HW_ATL_TPS_DESC_RATE_EN_SHIFT,
enable);
}
void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 rate_int)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_X_ADR(desc),
HW_ATL_TPS_DESC_RATE_X_MSK,
HW_ATL_TPS_DESC_RATE_X_SHIFT,
rate_int);
}
void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 rate_frac)
{
aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_Y_ADR(desc),
HW_ATL_TPS_DESC_RATE_Y_MSK,
HW_ATL_TPS_DESC_RATE_Y_SHIFT,
rate_frac);
}
/* tx */
void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
{

16
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
View File

@ -710,6 +710,22 @@ void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
u32 tx_pkt_shed_tc_data_weight,
u32 tc);
/* set tx descriptor rate mode */
void hw_atl_tps_tx_desc_rate_mode_set(struct aq_hw_s *aq_hw,
const u32 rate_mode);
/* set tx packet scheduler descriptor rate enable */
void hw_atl_tps_tx_desc_rate_en_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 enable);
/* set tx packet scheduler descriptor rate integral value */
void hw_atl_tps_tx_desc_rate_x_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 rate_int);
/* set tx packet scheduler descriptor rate fractional value */
void hw_atl_tps_tx_desc_rate_y_set(struct aq_hw_s *aq_hw, const u32 desc,
const u32 rate_frac);
/* tx */
/* set tx register reset disable */

70
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
View File

@ -2056,6 +2056,24 @@
/* default value of bitfield tx_tc_mode */
#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0
/* tx tx_desc_rate_mode bitfield definitions
* preprocessor definitions for the bitfield "tx_desc_rate_mode".
* port="pif_tps_desc_rate_mode_i"
*/
/* register address for bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR 0x00007900
/* bitmask for bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK 0x00000080
/* inverted bitmask for bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN 0xFFFFFF7F
/* lower bit position of bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT 7
/* width of bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH 1
/* default value of bitfield tx_desc_rate_mode */
#define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT 0x0
/* tx tx_buf_en bitfield definitions
* preprocessor definitions for the bitfield "tx_buf_en".
* port="pif_tpb_tx_buf_en_i"
@ -2275,6 +2293,58 @@
/* default value of bitfield data_tc_arb_mode */
#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
/* tx desc{r}_rate_en bitfield definitions
* preprocessor definitions for the bitfield "desc{r}_rate_en".
* port="pif_tps_desc_rate_en_i[0]"
*/
/* register address for bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) (0x00007408 + (desc) * 0x10)
/* bitmask for bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_MSK 0x80000000
/* inverted bitmask for bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_MSKN 0x7FFFFFFF
/* lower bit position of bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_SHIFT 31
/* width of bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_WIDTH 1
/* default value of bitfield desc{r}_rate_en */
#define HW_ATL_TPS_DESC_RATE_EN_DEFAULT 0x0
/* tx desc{r}_rate_x bitfield definitions
* preprocessor definitions for the bitfield "desc{r}_rate_x".
* port="pif_tps_desc0_rate_x"
*/
/* register address for bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_ADR(desc) (0x00007408 + (desc) * 0x10)
/* bitmask for bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_MSK 0x03FF0000
/* inverted bitmask for bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_MSKN 0xFC00FFFF
/* lower bit position of bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_SHIFT 16
/* width of bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_WIDTH 10
/* default value of bitfield desc{r}_rate_x */
#define HW_ATL_TPS_DESC_RATE_X_DEFAULT 0x0
/* tx desc{r}_rate_y bitfield definitions
* preprocessor definitions for the bitfield "desc{r}_rate_y".
* port="pif_tps_desc0_rate_y"
*/
/* register address for bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) (0x00007408 + (desc) * 0x10)
/* bitmask for bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_MSK 0x00003FFF
/* inverted bitmask for bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_MSKN 0xFFFFC000
/* lower bit position of bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_SHIFT 0
/* width of bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_WIDTH 14
/* default value of bitfield desc{r}_rate_y */
#define HW_ATL_TPS_DESC_RATE_Y_DEFAULT 0x0
/* tx desc_rate_ta_rst bitfield definitions
* preprocessor definitions for the bitfield "desc_rate_ta_rst".
* port="pif_tps_desc_rate_ta_rst_i"

9
drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c
View File

@ -135,6 +135,8 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
unsigned int prio = 0U;
u32 tc = 0U;
hw_atl_b0_hw_init_tx_tc_rate_limit(self);
/* TPS Descriptor rate init */
hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
@ -143,7 +145,6 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
/* TPS TC credits init */
hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
tx_buff_size /= cfg->tcs;
@ -155,8 +156,6 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF0,
tc);
hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, 0x640, tc);
hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, tc);
hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, tc);
/* Tx buf size TC0 */
hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
@ -215,8 +214,10 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self,
static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self)
{
struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
/* Tx TC/RSS number config */
hw_atl_tpb_tps_tx_tc_mode_set(self, self->aq_nic_cfg->tc_mode);
hw_atl_tpb_tps_tx_tc_mode_set(self, nic_cfg->tc_mode);
hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);