mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-19 15:29:14 +07:00
octeontx2-af: Add mailbox IRQ and msg handlers
This patch adds support for mailbox interrupt and message handling. Mapped mailbox region and registered a workqueue for message handling. Enabled mailbox IRQ of RVU PFs and registered a interrupt handler. When IRQ is triggered work is added to the mbox workqueue for msgs to get processed. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
021e2e53b8
commit
7304ac4567
@ -33,6 +33,8 @@
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# error "incorrect mailbox area sizes"
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#endif
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#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
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#define MBOX_RSP_TIMEOUT 1000 /* in ms, Time to wait for mbox response */
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#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
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@ -90,8 +92,9 @@ struct mbox_msghdr {
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void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
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void otx2_mbox_destroy(struct otx2_mbox *mbox);
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int otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev,
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void *reg_base, int direction, int ndevs);
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int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
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struct pci_dev *pdev, void __force *reg_base,
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int direction, int ndevs);
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void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
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int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
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int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
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@ -115,7 +118,7 @@ static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
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#define MBOX_MSG_MAX 0xFFFF
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#define MBOX_MESSAGES \
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M(READY, 0x001, msg_req, msg_rsp)
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M(READY, 0x001, msg_req, ready_msg_rsp)
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enum {
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#define M(_name, _id, _1, _2) MBOX_MSG_ ## _name = _id,
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@ -139,4 +142,9 @@ struct msg_rsp {
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struct mbox_msghdr hdr;
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};
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struct ready_msg_rsp {
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struct mbox_msghdr hdr;
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u16 sclk_feq; /* SCLK frequency */
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};
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#endif /* MBOX_H */
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@ -257,6 +257,245 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
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return 0;
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}
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static int rvu_process_mbox_msg(struct rvu *rvu, int devid,
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struct mbox_msghdr *req)
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{
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/* Check if valid, if not reply with a invalid msg */
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if (req->sig != OTX2_MBOX_REQ_SIG)
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goto bad_message;
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if (req->id == MBOX_MSG_READY)
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return 0;
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bad_message:
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otx2_reply_invalid_msg(&rvu->mbox, devid, req->pcifunc,
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req->id);
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return -ENODEV;
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}
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static void rvu_mbox_handler(struct work_struct *work)
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{
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struct rvu_work *mwork = container_of(work, struct rvu_work, work);
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struct rvu *rvu = mwork->rvu;
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struct otx2_mbox_dev *mdev;
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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struct otx2_mbox *mbox;
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int offset, id, err;
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u16 pf;
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mbox = &rvu->mbox;
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pf = mwork - rvu->mbox_wrk;
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mdev = &mbox->dev[pf];
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/* Process received mbox messages */
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req_hdr = mdev->mbase + mbox->rx_start;
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if (req_hdr->num_msgs == 0)
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return;
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offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
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for (id = 0; id < req_hdr->num_msgs; id++) {
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msg = mdev->mbase + offset;
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/* Set which PF sent this message based on mbox IRQ */
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msg->pcifunc &= ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
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msg->pcifunc |= (pf << RVU_PFVF_PF_SHIFT);
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err = rvu_process_mbox_msg(rvu, pf, msg);
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if (!err) {
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offset = mbox->rx_start + msg->next_msgoff;
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continue;
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}
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if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
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dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
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err, otx2_mbox_id2name(msg->id), msg->id, pf,
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(msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
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else
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dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
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err, otx2_mbox_id2name(msg->id), msg->id, pf);
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}
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/* Send mbox responses to PF */
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otx2_mbox_msg_send(mbox, pf);
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}
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static int rvu_mbox_init(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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void __iomem *hwbase = NULL;
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struct rvu_work *mwork;
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u64 bar4_addr;
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int err, pf;
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rvu->mbox_wq = alloc_workqueue("rvu_afpf_mailbox",
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WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
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hw->total_pfs);
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if (!rvu->mbox_wq)
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return -ENOMEM;
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rvu->mbox_wrk = devm_kcalloc(rvu->dev, hw->total_pfs,
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sizeof(struct rvu_work), GFP_KERNEL);
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if (!rvu->mbox_wrk) {
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err = -ENOMEM;
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goto exit;
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}
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/* Map mbox region shared with PFs */
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bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR);
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/* Mailbox is a reserved memory (in RAM) region shared between
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* RVU devices, shouldn't be mapped as device memory to allow
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* unaligned accesses.
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*/
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hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * hw->total_pfs);
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if (!hwbase) {
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dev_err(rvu->dev, "Unable to map mailbox region\n");
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err = -ENOMEM;
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goto exit;
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}
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err = otx2_mbox_init(&rvu->mbox, hwbase, rvu->pdev, rvu->afreg_base,
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MBOX_DIR_AFPF, hw->total_pfs);
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if (err)
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goto exit;
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for (pf = 0; pf < hw->total_pfs; pf++) {
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mwork = &rvu->mbox_wrk[pf];
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mwork->rvu = rvu;
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INIT_WORK(&mwork->work, rvu_mbox_handler);
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}
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return 0;
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exit:
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if (hwbase)
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iounmap((void __iomem *)hwbase);
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destroy_workqueue(rvu->mbox_wq);
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return err;
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}
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static void rvu_mbox_destroy(struct rvu *rvu)
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{
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if (rvu->mbox_wq) {
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flush_workqueue(rvu->mbox_wq);
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destroy_workqueue(rvu->mbox_wq);
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rvu->mbox_wq = NULL;
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}
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if (rvu->mbox.hwbase)
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iounmap((void __iomem *)rvu->mbox.hwbase);
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otx2_mbox_destroy(&rvu->mbox);
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}
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static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
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{
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struct rvu *rvu = (struct rvu *)rvu_irq;
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struct otx2_mbox_dev *mdev;
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struct otx2_mbox *mbox;
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struct mbox_hdr *hdr;
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u64 intr;
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u8 pf;
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intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
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/* Clear interrupts */
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rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
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/* Sync with mbox memory region */
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smp_wmb();
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for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
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if (intr & (1ULL << pf)) {
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mbox = &rvu->mbox;
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mdev = &mbox->dev[pf];
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hdr = mdev->mbase + mbox->rx_start;
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if (hdr->num_msgs)
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queue_work(rvu->mbox_wq,
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&rvu->mbox_wrk[pf].work);
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}
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}
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return IRQ_HANDLED;
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}
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static void rvu_enable_mbox_intr(struct rvu *rvu)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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/* Clear spurious irqs, if any */
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rvu_write64(rvu, BLKADDR_RVUM,
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RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
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/* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
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rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
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INTR_MASK(hw->total_pfs) & ~1ULL);
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}
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static void rvu_unregister_interrupts(struct rvu *rvu)
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{
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int irq;
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/* Disable the Mbox interrupt */
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rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
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INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
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for (irq = 0; irq < rvu->num_vec; irq++) {
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if (rvu->irq_allocated[irq])
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free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
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}
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pci_free_irq_vectors(rvu->pdev);
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rvu->num_vec = 0;
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}
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static int rvu_register_interrupts(struct rvu *rvu)
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{
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int ret;
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rvu->num_vec = pci_msix_vec_count(rvu->pdev);
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rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
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NAME_SIZE, GFP_KERNEL);
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if (!rvu->irq_name)
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return -ENOMEM;
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rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
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sizeof(bool), GFP_KERNEL);
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if (!rvu->irq_allocated)
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return -ENOMEM;
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/* Enable MSI-X */
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ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
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rvu->num_vec, PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_err(rvu->dev,
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"RVUAF: Request for %d msix vectors failed, ret %d\n",
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rvu->num_vec, ret);
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return ret;
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}
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/* Register mailbox interrupt handler */
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sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
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ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
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rvu_mbox_intr_handler, 0,
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&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
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if (ret) {
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dev_err(rvu->dev,
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"RVUAF: IRQ registration failed for mbox irq\n");
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goto fail;
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}
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rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
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/* Enable mailbox interrupts from all PFs */
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rvu_enable_mbox_intr(rvu);
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return 0;
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fail:
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pci_free_irq_vectors(rvu->pdev);
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return ret;
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}
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static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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@ -319,8 +558,21 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (err)
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goto err_release_regions;
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err = rvu_mbox_init(rvu);
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if (err)
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goto err_hwsetup;
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err = rvu_register_interrupts(rvu);
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if (err)
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goto err_mbox;
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return 0;
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err_mbox:
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rvu_mbox_destroy(rvu);
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err_hwsetup:
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rvu_reset_all_blocks(rvu);
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rvu_free_hw_resources(rvu);
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err_release_regions:
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pci_release_regions(pdev);
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err_disable_device:
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@ -336,6 +588,8 @@ static void rvu_remove(struct pci_dev *pdev)
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{
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struct rvu *rvu = pci_get_drvdata(pdev);
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rvu_unregister_interrupts(rvu);
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rvu_mbox_destroy(rvu);
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rvu_reset_all_blocks(rvu);
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rvu_free_hw_resources(rvu);
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@ -12,6 +12,7 @@
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#define RVU_H
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#include "rvu_struct.h"
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#include "mbox.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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@ -23,6 +24,17 @@
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#define NAME_SIZE 32
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/* PF_FUNC */
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#define RVU_PFVF_PF_SHIFT 10
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#define RVU_PFVF_PF_MASK 0x3F
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#define RVU_PFVF_FUNC_SHIFT 0
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#define RVU_PFVF_FUNC_MASK 0x3FF
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struct rvu_work {
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struct work_struct work;
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struct rvu *rvu;
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};
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struct rsrc_bmap {
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unsigned long *bmap; /* Pointer to resource bitmap */
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u16 max; /* Max resource id or count */
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@ -57,6 +69,16 @@ struct rvu {
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struct pci_dev *pdev;
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struct device *dev;
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struct rvu_hwinfo *hw;
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/* Mbox */
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struct otx2_mbox mbox;
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struct rvu_work *mbox_wrk;
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struct workqueue_struct *mbox_wq;
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/* MSI-X */
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u16 num_vec;
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char *irq_name;
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bool *irq_allocated;
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};
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static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
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@ -31,4 +31,26 @@ enum rvu_block_addr_e {
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BLK_COUNT = 0xfULL,
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};
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/* RVU Admin function Interrupt Vector Enumeration */
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enum rvu_af_int_vec_e {
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RVU_AF_INT_VEC_POISON = 0x0,
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RVU_AF_INT_VEC_PFFLR = 0x1,
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RVU_AF_INT_VEC_PFME = 0x2,
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RVU_AF_INT_VEC_GEN = 0x3,
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RVU_AF_INT_VEC_MBOX = 0x4,
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};
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/**
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* RVU PF Interrupt Vector Enumeration
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*/
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enum rvu_pf_int_vec_e {
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RVU_PF_INT_VEC_VFFLR0 = 0x0,
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RVU_PF_INT_VEC_VFFLR1 = 0x1,
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RVU_PF_INT_VEC_VFME0 = 0x2,
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RVU_PF_INT_VEC_VFME1 = 0x3,
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RVU_PF_INT_VEC_VFPF_MBOX0 = 0x4,
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RVU_PF_INT_VEC_VFPF_MBOX1 = 0x5,
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RVU_PF_INT_VEC_AFPF_MBOX = 0x6,
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};
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#endif /* RVU_STRUCT_H */
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