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hw-breakpoints: modify Ptrace routines to access breakpoint registers
This patch modifies the ptrace code to use the new wrapper routines around the debug/breakpoint registers. [ Impact: adapt x86 ptrace to the new breakpoint Api ] Original-patch-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com> Signed-off-by: Maneesh Soni <maneesh@linux.vnet.ibm.com> Reviewed-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
This commit is contained in:
K.Prasad
Frederic Weisbecker
parent
da0cdc14f5
commit
72f674d203
@ -34,6 +34,7 @@
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#include <asm/prctl.h>
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#include <asm/proto.h>
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#include <asm/ds.h>
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#include <asm/hw_breakpoint.h>
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#include <trace/syscall.h>
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@ -136,11 +137,6 @@ static int set_segment_reg(struct task_struct *task,
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return 0;
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}
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static unsigned long debugreg_addr_limit(struct task_struct *task)
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{
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return TASK_SIZE - 3;
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}
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#else /* CONFIG_X86_64 */
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#define FLAG_MASK (FLAG_MASK_32 | X86_EFLAGS_NT)
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@ -265,15 +261,6 @@ static int set_segment_reg(struct task_struct *task,
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return 0;
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}
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static unsigned long debugreg_addr_limit(struct task_struct *task)
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{
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#ifdef CONFIG_IA32_EMULATION
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if (test_tsk_thread_flag(task, TIF_IA32))
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return IA32_PAGE_OFFSET - 3;
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#endif
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return TASK_SIZE_MAX - 7;
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}
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#endif /* CONFIG_X86_32 */
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static unsigned long get_flags(struct task_struct *task)
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@ -464,95 +451,159 @@ static int genregs_set(struct task_struct *target,
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}
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/*
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* This function is trivial and will be inlined by the compiler.
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* Having it separates the implementation details of debug
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* registers from the interface details of ptrace.
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* Decode the length and type bits for a particular breakpoint as
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* stored in debug register 7. Return the "enabled" status.
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*/
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static unsigned long ptrace_get_debugreg(struct task_struct *child, int n)
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static int decode_dr7(unsigned long dr7, int bpnum, unsigned *len,
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unsigned *type)
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{
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switch (n) {
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case 0: return child->thread.debugreg[0];
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case 1: return child->thread.debugreg[1];
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case 2: return child->thread.debugreg[2];
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case 3: return child->thread.debugreg[3];
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case 6: return child->thread.debugreg6;
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case 7: return child->thread.debugreg7;
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}
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return 0;
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int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
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*len = (bp_info & 0xc) | 0x40;
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*type = (bp_info & 0x3) | 0x80;
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return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
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}
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static int ptrace_set_debugreg(struct task_struct *child,
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int n, unsigned long data)
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static void ptrace_triggered(struct hw_breakpoint *bp, struct pt_regs *regs)
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{
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struct thread_struct *thread = &(current->thread);
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int i;
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if (unlikely(n == 4 || n == 5))
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return -EIO;
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if (n < 4 && unlikely(data >= debugreg_addr_limit(child)))
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return -EIO;
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switch (n) {
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case 0: child->thread.debugreg[0] = data; break;
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case 1: child->thread.debugreg[1] = data; break;
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case 2: child->thread.debugreg[2] = data; break;
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case 3: child->thread.debugreg[3] = data; break;
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case 6:
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if ((data & ~0xffffffffUL) != 0)
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return -EIO;
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child->thread.debugreg6 = data;
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/*
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* Store in the virtual DR6 register the fact that the breakpoint
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* was hit so the thread's debugger will see it.
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*/
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for (i = 0; i < hbp_kernel_pos; i++)
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/*
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* We will check bp->info.address against the address stored in
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* thread's hbp structure and not debugreg[i]. This is to ensure
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* that the corresponding bit for 'i' in DR7 register is enabled
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*/
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if (bp->info.address == thread->hbp[i]->info.address)
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break;
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case 7:
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/*
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* Sanity-check data. Take one half-byte at once with
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* check = (val >> (16 + 4*i)) & 0xf. It contains the
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* R/Wi and LENi bits; bits 0 and 1 are R/Wi, and bits
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* 2 and 3 are LENi. Given a list of invalid values,
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* we do mask |= 1 << invalid_value, so that
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* (mask >> check) & 1 is a correct test for invalid
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* values.
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*
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* R/Wi contains the type of the breakpoint /
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* watchpoint, LENi contains the length of the watched
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* data in the watchpoint case.
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*
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* The invalid values are:
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* - LENi == 0x10 (undefined), so mask |= 0x0f00. [32-bit]
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* - R/Wi == 0x10 (break on I/O reads or writes), so
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* mask |= 0x4444.
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* - R/Wi == 0x00 && LENi != 0x00, so we have mask |=
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* 0x1110.
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*
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* Finally, mask = 0x0f00 | 0x4444 | 0x1110 == 0x5f54.
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*
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* See the Intel Manual "System Programming Guide",
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* 15.2.4
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*
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* Note that LENi == 0x10 is defined on x86_64 in long
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* mode (i.e. even for 32-bit userspace software, but
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* 64-bit kernel), so the x86_64 mask value is 0x5454.
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* See the AMD manual no. 24593 (AMD64 System Programming)
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thread->debugreg6 |= (DR_TRAP0 << i);
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}
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/*
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* Handle ptrace writes to debug register 7.
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*/
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#ifdef CONFIG_X86_32
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#define DR7_MASK 0x5f54
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#else
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#define DR7_MASK 0x5554
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#endif
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static int ptrace_write_dr7(struct task_struct *tsk, unsigned long data)
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{
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struct thread_struct *thread = &(tsk->thread);
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unsigned long old_dr7 = thread->debugreg7;
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int i, orig_ret = 0, rc = 0;
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int enabled, second_pass = 0;
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unsigned len, type;
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struct hw_breakpoint *bp;
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data &= ~DR_CONTROL_RESERVED;
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for (i = 0; i < 4; i++)
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if ((DR7_MASK >> ((data >> (16 + 4*i)) & 0xf)) & 1)
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return -EIO;
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child->thread.debugreg7 = data;
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if (data)
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set_tsk_thread_flag(child, TIF_DEBUG);
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else
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clear_tsk_thread_flag(child, TIF_DEBUG);
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restore:
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/*
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* Loop through all the hardware breakpoints, making the
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* appropriate changes to each.
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*/
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for (i = 0; i < HBP_NUM; i++) {
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enabled = decode_dr7(data, i, &len, &type);
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bp = thread->hbp[i];
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if (!enabled) {
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if (bp) {
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/* Don't unregister the breakpoints right-away,
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* unless all register_user_hw_breakpoint()
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* requests have succeeded. This prevents
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* any window of opportunity for debug
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* register grabbing by other users.
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*/
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if (!second_pass)
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continue;
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unregister_user_hw_breakpoint(tsk, bp);
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kfree(bp);
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}
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continue;
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}
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if (!bp) {
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rc = -ENOMEM;
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bp = kzalloc(sizeof(struct hw_breakpoint), GFP_KERNEL);
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if (bp) {
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bp->info.address = thread->debugreg[i];
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bp->triggered = ptrace_triggered;
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bp->info.len = len;
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bp->info.type = type;
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rc = register_user_hw_breakpoint(tsk, bp);
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if (rc)
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kfree(bp);
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}
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} else
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rc = modify_user_hw_breakpoint(tsk, bp);
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if (rc)
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break;
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}
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/*
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* Make a second pass to free the remaining unused breakpoints
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* or to restore the original breakpoints if an error occurred.
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*/
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if (!second_pass) {
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second_pass = 1;
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if (rc < 0) {
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orig_ret = rc;
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data = old_dr7;
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}
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goto restore;
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}
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return ((orig_ret < 0) ? orig_ret : rc);
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}
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return 0;
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/*
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* Handle PTRACE_PEEKUSR calls for the debug register area.
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*/
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unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
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{
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struct thread_struct *thread = &(tsk->thread);
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unsigned long val = 0;
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if (n < HBP_NUM)
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val = thread->debugreg[n];
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else if (n == 6)
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val = thread->debugreg6;
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else if (n == 7)
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val = thread->debugreg7;
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return val;
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}
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/*
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* Handle PTRACE_POKEUSR calls for the debug register area.
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*/
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int ptrace_set_debugreg(struct task_struct *tsk, int n, unsigned long val)
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{
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struct thread_struct *thread = &(tsk->thread);
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int rc = 0;
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/* There are no DR4 or DR5 registers */
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if (n == 4 || n == 5)
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return -EIO;
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if (n == 6) {
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tsk->thread.debugreg6 = val;
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goto ret_path;
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}
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if (n < HBP_NUM) {
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if (thread->hbp[n]) {
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if (arch_check_va_in_userspace(val,
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thread->hbp[n]->info.len) == 0) {
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rc = -EIO;
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goto ret_path;
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}
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thread->hbp[n]->info.address = val;
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}
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thread->debugreg[n] = val;
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}
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/* All that's left is DR7 */
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if (n == 7)
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rc = ptrace_write_dr7(tsk, val);
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ret_path:
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return rc;
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}
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/*
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