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Qualcomm ARM64 Updates for v5.3 Part 2

Browse Source 
* Add SDM845 Cheza support
 * Add TSENS controller and thermal zones for QCS404
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Merge tag 'qcom-arm64-for-5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 Updates for v5.3 Part 2

* Add SDM845 Cheza support
* Add TSENS controller and thermal zones for QCS404

* tag 'qcom-arm64-for-5.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: dts: qcom: qcs404: Add missing space for cooling-cells property
  arm64: dts: qcom: sdm845-cheza: add initial cheza dt
  arm64: dts: qcom: qcs404: Add thermal zones for each sensor
  arm64: dts: qcom: qcs404: Add tsens controller

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-06-27 23:26:40 -07:00
commit 72ce9b7cab
6 changed files with 2251 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/qcom/Makefile
View File

@ -7,6 +7,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb

272
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@ -34,6 +35,7 @@ CPU0: cpu@100 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
};
CPU1: cpu@101 {
@ -43,6 +45,7 @@ CPU1: cpu@101 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
};
CPU2: cpu@102 {
@ -52,6 +55,7 @@ CPU2: cpu@102 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
};
CPU3: cpu@103 {
@ -61,6 +65,7 @@ CPU3: cpu@103 {
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
};
L2_0: l2-cache {
@ -251,6 +256,16 @@ rpm_msg_ram: memory@60000 {
reg = <0x00060000 0x6000>;
};
qfprom: qfprom@a4000 {
compatible = "qcom,qfprom";
reg = <0x000a4000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_caldata: caldata@d0 {
reg = <0x1f8 0x14>;
};
};
rng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
@ -258,6 +273,16 @@ rng: rng@e3000 {
clock-names = "core";
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_caldata>;
nvmem-cell-names = "calib";
#qcom,sensors = <10>;
#thermal-sensor-cells = <1>;
};
remoteproc_cdsp: remoteproc@b00000 {
compatible = "qcom,qcs404-cdsp-pas";
reg = <0x00b00000 0x4040>;
@ -1043,4 +1068,251 @@ wcss_smp2p_in: slave-kernel {
#interrupt-cells = <2>;
};
};
thermal-zones {
aoss-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
trips {
aoss_alert0: trip-point@0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
};
};
};
q6-hvx-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
trips {
q6_hvx_alert0: trip-point@0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
};
};
};
lpass-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
trips {
lpass_alert0: trip-point@0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
};
};
};
wlan-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
trips {
wlan_alert0: trip-point@0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cluster-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
trips {
cluster_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cluster_alert1: trip-point@1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cluster_crit: cluster_crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cluster_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
trips {
cpu0_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu0_alert1: trip-point@1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
trips {
cpu1_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu1_alert1: trip-point@1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
trips {
cpu2_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu2_alert1: trip-point@1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
trips {
cpu3_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu3_alert1: trip-point@1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
trips {
gpu_alert0: trip-point@0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
};

238
arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts Normal file
View File

@ -0,0 +1,238 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev1)";
compatible = "google,cheza-rev1", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"",
"PEN_RST_L",
"PEN_IRQ_L",
"",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};

238
arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts Normal file
View File

@ -0,0 +1,238 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev2)";
compatible = "google,cheza-rev2", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};

174
arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts Normal file
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@ -0,0 +1,174 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev3+)";
compatible = "google,cheza", "qcom,sdm845";
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID0",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID2",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID1",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID0",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID1",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
* call it BIOS_FLASH_WP_R_L.
*/
"AP_FLASH_WP_L",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID0",
"AP_RAM_ID1",
"RFFE1_DATA",
"RFFE1_CLK";
};

1326
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi Normal file
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