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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 14:06:48 +07:00
iwlwifi: add tm commands for indirect register access
Create new testmode commands to suppot indirect access of peripheral register. - IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32 - IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32 Meanwhile, add affix "DIRECT" into original register access commands for better discrimination with new commands. - IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32 - IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32 - IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8 Signed-off-by: Kenny Hsu <kenny.hsu@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
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27f6cbecbf
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@ -276,7 +276,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
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IWL_INFO(priv, "testmode register access command offset 0x%x\n", ofs);
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switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
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case IWL_TM_CMD_APP2DEV_REG_READ32:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
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val32 = iwl_read32(bus(priv), ofs);
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IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
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@ -291,7 +291,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
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IWL_DEBUG_INFO(priv,
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"Error sending msg : %d\n", status);
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break;
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case IWL_TM_CMD_APP2DEV_REG_WRITE32:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32:
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if (!tb[IWL_TM_ATTR_REG_VALUE32]) {
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IWL_DEBUG_INFO(priv,
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"Error finding value to write\n");
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@ -302,7 +302,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
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iwl_write32(bus(priv), ofs, val32);
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}
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break;
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case IWL_TM_CMD_APP2DEV_REG_WRITE8:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
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if (!tb[IWL_TM_ATTR_REG_VALUE8]) {
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IWL_DEBUG_INFO(priv, "Error finding value to write\n");
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return -ENOMSG;
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@ -312,6 +312,32 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
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iwl_write8(bus(priv), ofs, val8);
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}
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break;
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case IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32:
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val32 = iwl_read_prph(bus(priv), ofs);
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IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
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skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20);
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if (!skb) {
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IWL_DEBUG_INFO(priv, "Error allocating memory\n");
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return -ENOMEM;
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}
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NLA_PUT_U32(skb, IWL_TM_ATTR_REG_VALUE32, val32);
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status = cfg80211_testmode_reply(skb);
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if (status < 0)
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IWL_DEBUG_INFO(priv,
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"Error sending msg : %d\n", status);
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break;
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case IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32:
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if (!tb[IWL_TM_ATTR_REG_VALUE32]) {
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IWL_DEBUG_INFO(priv,
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"Error finding value to write\n");
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return -ENOMSG;
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} else {
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val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
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IWL_INFO(priv, "32bit value to write 0x%x\n", val32);
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iwl_write_prph(bus(priv), ofs, val32);
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}
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break;
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default:
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IWL_DEBUG_INFO(priv, "Unknown testmode register command ID\n");
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return -ENOSYS;
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@ -665,9 +691,11 @@ int iwlagn_mac_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
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IWL_DEBUG_INFO(priv, "testmode cmd to uCode\n");
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result = iwl_testmode_ucode(hw, tb);
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break;
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case IWL_TM_CMD_APP2DEV_REG_READ32:
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case IWL_TM_CMD_APP2DEV_REG_WRITE32:
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case IWL_TM_CMD_APP2DEV_REG_WRITE8:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32:
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
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case IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32:
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case IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32:
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IWL_DEBUG_INFO(priv, "testmode cmd to register\n");
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result = iwl_testmode_reg(hw, tb);
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break;
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@ -76,9 +76,9 @@
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* the actual uCode host command ID is carried with
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* IWL_TM_ATTR_UCODE_CMD_ID
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*
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* @IWL_TM_CMD_APP2DEV_REG_READ32:
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* @IWL_TM_CMD_APP2DEV_REG_WRITE32:
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* @IWL_TM_CMD_APP2DEV_REG_WRITE8:
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* @IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
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* @IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32:
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* @IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
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* commands from user applicaiton to access register
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*
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* @IWL_TM_CMD_APP2DEV_GET_DEVICENAME: retrieve device name
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@ -107,12 +107,16 @@
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* commands from user application to own change the ownership of the uCode
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* if application has the ownership, the only host command from
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* testmode will deliver to uCode. Default owner is driver
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* @IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32:
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* @IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32:
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* commands from user applicaiton to indirectly access peripheral register
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*
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*/
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enum iwl_tm_cmd_t {
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IWL_TM_CMD_APP2DEV_UCODE = 1,
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IWL_TM_CMD_APP2DEV_REG_READ32 = 2,
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IWL_TM_CMD_APP2DEV_REG_WRITE32 = 3,
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IWL_TM_CMD_APP2DEV_REG_WRITE8 = 4,
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IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32 = 2,
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IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32 = 3,
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IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8 = 4,
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IWL_TM_CMD_APP2DEV_GET_DEVICENAME = 5,
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IWL_TM_CMD_APP2DEV_LOAD_INIT_FW = 6,
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IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB = 7,
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@ -126,7 +130,9 @@ enum iwl_tm_cmd_t {
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IWL_TM_CMD_DEV2APP_UCODE_RX_PKT = 15,
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IWL_TM_CMD_DEV2APP_EEPROM_RSP = 16,
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IWL_TM_CMD_APP2DEV_OWNERSHIP = 17,
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IWL_TM_CMD_MAX = 18,
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IWL_TM_CMD_APP2DEV_INDIRECT_REG_READ32 = 18,
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IWL_TM_CMD_APP2DEV_INDIRECT_REG_WRITE32 = 19,
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IWL_TM_CMD_MAX = 20,
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};
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/*
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