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ARM64: dts: Add Realtek RTD1295 and Zidoo X9S
Add initial device trees for the RTD1295 SoC and the Zidoo X9S TV box. The CPUs lack the enable-method property because the vendor device tree uses a custom "rtk-spin-table" method and "psci" did not appear to work. The UARTs lack the interrupts properties because the vendor device tree connects them to a custom interrupt controller. earlycon works without. A list of memory reservations is adopted from v1.2.11 vendor device tree: 0x02200000 can be used for an initrd, 0x01b00000 is audio-related; ion-related 0x02600000, 0x02c00000 and 0x11000000 are left out; 0x10000000 is used for sharing the U-Boot environment; others remain to be investigated. Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -14,6 +14,7 @@ dts-dirs += marvell
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dts-dirs += mediatek
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dts-dirs += nvidia
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dts-dirs += qcom
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dts-dirs += realtek
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dts-dirs += renesas
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dts-dirs += rockchip
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dts-dirs += socionext
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5
arch/arm64/boot/dts/realtek/Makefile
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5
arch/arm64/boot/dts/realtek/Makefile
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@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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42
arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts
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42
arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2016-2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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/memreserve/ 0x0000000000000000 0x0000000000030000;
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/memreserve/ 0x000000000001f000 0x0000000000001000;
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/memreserve/ 0x0000000000030000 0x00000000000d0000;
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/memreserve/ 0x0000000001b00000 0x00000000004be000;
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/memreserve/ 0x0000000001ffe000 0x0000000000004000;
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#include "rtd1295.dtsi"
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/ {
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compatible = "zidoo,x9s", "realtek,rtd1295";
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model = "Zidoo X9S";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x80000000>;
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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131
arch/arm64/boot/dts/realtek/rtd1295.dtsi
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131
arch/arm64/boot/dts/realtek/rtd1295.dtsi
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@ -0,0 +1,131 @@
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/*
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* Realtek RTD1295 SoC
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*
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* Copyright (c) 2016-2017 Andreas Färber
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "realtek,rtd1295";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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tee@10100000 {
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reg = <0x10100000 0xf00000>;
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no-map;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Exclude up to 2 GiB of RAM */
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ranges = <0x80000000 0x80000000 0x80000000>;
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uart0: serial@98007800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x98007800 0x400>,
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<0x98007000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <27000000>;
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status = "disabled";
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};
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uart1: serial@9801b200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9801b200 0x100>,
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<0x9801b00c 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <432000000>;
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status = "disabled";
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};
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uart2: serial@9801b400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9801b400 0x100>,
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<0x9801b00c 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <432000000>;
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status = "disabled";
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};
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gic: interrupt-controller@ff011000 {
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compatible = "arm,gic-400";
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reg = <0xff011000 0x1000>,
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<0xff012000 0x2000>,
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<0xff014000 0x2000>,
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<0xff016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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