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arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 master
This commit adds an initial Device Tree description for the CP110 master that is found in the Armada 7K and 8K SoCs. This initial description describes: - the system controller (to provide clocks) - three PCIe interfaces - the SATA interface - the I2C controllers - the SPI controllers For the record, the organization of the SoCs is as follows: - 7020: dual-core AP, one CP110 (master) - 7040: quad-core AP, one CP110 (master) - 8020: dual-core AP, two CP110s (master and slave) - 8040: quad-core AP, two CP110s (master and slave) For this reason, all of the 7020, 7040, 8020 and 8040 include armada-cp110-master.dtsi. When support for the second CP110 (slave) used in 8020 and 8040 will be added, the .dtsi files for those SoCs will in addition include armada-cp110-slave.dtsi. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
Thomas Petazzoni
Gregory CLEMENT
parent
d8b330a3e3
commit
728dacc7f4
@ -46,6 +46,7 @@
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*/
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#include "armada-ap806-dual.dtsi"
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#include "armada-cp110-master.dtsi"
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/ {
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model = "Marvell Armada 7020";
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@ -46,6 +46,7 @@
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*/
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#include "armada-ap806-quad.dtsi"
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#include "armada-cp110-master.dtsi"
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/ {
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model = "Marvell Armada 7040";
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@ -46,6 +46,7 @@
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*/
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#include "armada-ap806-dual.dtsi"
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#include "armada-cp110-master.dtsi"
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/ {
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model = "Marvell Armada 8020";
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@ -46,6 +46,7 @@
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*/
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#include "armada-ap806-quad.dtsi"
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#include "armada-cp110-master.dtsi"
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/ {
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model = "Marvell Armada 8040";
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228
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
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228
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
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@ -0,0 +1,228 @@
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Device Tree file for Marvell Armada CP110 Master.
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*/
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/ {
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cp110-master {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf2000000 0x2000000>;
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cpm_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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reg = <0x440000 0x1000>;
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#clock-cells = <2>;
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core-clock-output-names =
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"cpm-apll", "cpm-ppv2-core", "cpm-eip",
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"cpm-core", "cpm-nand-core";
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gate-clock-output-names =
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"cpm-audio", "cpm-communit", "cpm-nand",
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"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
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"cpm-mg-core", "cpm-xor1", "cpm-xor0",
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"cpm-gop-dp", "none", "cpm-pcie_x10",
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"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
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"cpm-sata", "cpm-sata-usb", "cpm-main",
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"cpm-sd-mmc", "none", "none",
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"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
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"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
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};
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cpm_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 15>;
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status = "disabled";
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};
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cpm_usb3_0: usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 22>;
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status = "disabled";
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};
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cpm_usb3_1: usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 23>;
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status = "disabled";
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};
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cpm_spi0: spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cell-index = <1>;
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clocks = <&cpm_syscon0 0 3>;
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status = "disabled";
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};
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cpm_spi1: spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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clocks = <&cpm_syscon0 1 21>;
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status = "disabled";
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};
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cpm_i2c0: i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 21>;
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status = "disabled";
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};
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cpm_i2c1: i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_syscon0 1 21>;
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status = "disabled";
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};
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};
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cpm_pcie0: pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2600000 0 0x10000>,
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<0 0xf6f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 13>;
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status = "disabled";
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};
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cpm_pcie1: pcie@f2620000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2620000 0 0x10000>,
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<0 0xf7f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 11>;
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status = "disabled";
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};
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cpm_pcie2: pcie@f2640000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2640000 0 0x10000>,
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<0 0xf8f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 12>;
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status = "disabled";
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};
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};
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};
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