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drm/amd/display: Add DCN2 changes to DML

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Update DML (Display Mode Lib) to support DCN2

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2019-02-22 09:59:43 -05:00 committed by Alex Deucher
parent bff65b7781
commit 728c06986a
11 changed files with 8693 additions and 4 deletions
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7
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
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@ -31,6 +31,7 @@
#include "resource.h"
#include "dcn10/dcn10_resource.h"
#include "dcn10/dcn10_hubbub.h"
#include "dml/dml1_display_rq_dlg_calc.h"
#include "dcn_calc_math.h"
@ -52,7 +53,13 @@
* remain as-is as it provides us with a guarantee from HW that it is correct.
*/
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
/* Defaults from spreadsheet rev#247.
* RV2 delta: dram_clock_change_latency, max_num_dpp
*/
#else
/* Defaults from spreadsheet rev#247 */
#endif
const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
.sr_exit_time = 17, /*us*/

15
drivers/gpu/drm/amd/display/dc/dml/Makefile
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@ -33,13 +33,24 @@ endif
dml_ccflags := -mhard-float -msse $(cc_stack_align)
CFLAGS_display_mode_lib.o := $(dml_ccflags)
CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
CFLAGS_display_mode_vba.o := $(dml_ccflags)
ifdef CONFIG_DRM_AMD_DC_DCN2_0
CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
endif
ifdef CONFIG_DRM_AMD_DCN3AG
CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags)
endif
CFLAGS_dml1_display_rq_dlg_calc.o := $(dml_ccflags)
CFLAGS_display_rq_dlg_helpers.o := $(dml_ccflags)
CFLAGS_dml_common_defs.o := $(dml_ccflags)
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
dml_common_defs.o
dml_common_defs.o display_mode_vba.o
ifdef CONFIG_DRM_AMD_DC_DCN2_0
DML += dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
endif
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))

5104
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c Normal file
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32
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.h Normal file
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@ -0,0 +1,32 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCN20_DISPLAY_MODE_VBA_H_
#define _DCN20_DISPLAY_MODE_VBA_H_
void dml20_recalculate(struct display_mode_lib *mode_lib);
void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
#endif

1698
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c Normal file
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File diff suppressed because it is too large Load Diff

71
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h Normal file
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@ -0,0 +1,71 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML20_DISPLAY_RQ_DLG_CALC_H__
#define __DML20_DISPLAY_RQ_DLG_CALC_H__
#include "../dml_common_defs.h"
#include "../display_rq_dlg_helpers.h"
struct display_mode_lib;
// Function: dml_rq_dlg_get_rq_reg
// Main entry point for test to get the register values out of this DML class.
// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
// and then populate the rq_regs struct
// Input:
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
// Output:
// rq_regs - struct that holds all the RQ registers field value.
// See also: <display_rq_regs_st>
void dml20_rq_dlg_get_rq_reg(
struct display_mode_lib *mode_lib,
display_rq_regs_st *rq_regs,
const display_pipe_params_st pipe_param);
// Function: dml_rq_dlg_get_dlg_reg
// Calculate and return DLG and TTU register struct given the system setting
// Output:
// dlg_regs - output DLG register struct
// ttu_regs - output DLG TTU register struct
// Input:
// e2e_pipe_param - "compacted" array of e2e pipe param struct
// num_pipes - num of active "pipe" or "route"
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
// Added for legacy or unrealistic timing tests.
void dml20_rq_dlg_get_dlg_reg(
struct display_mode_lib *mode_lib,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
const bool pstate_en);
#endif

22
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
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@ -25,6 +25,19 @@
#include "display_mode_lib.h"
#include "dc_features.h"
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#include "dcn20/display_mode_vba_20.h"
#include "dcn20/display_rq_dlg_calc_20.h"
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
const struct dml_funcs dml20_funcs = {
.validate = dml20_ModeSupportAndSystemConfigurationFull,
.recalculate = dml20_recalculate,
.rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg,
.rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg
};
#endif
void dml_init_instance(struct display_mode_lib *lib,
const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
@ -34,6 +47,15 @@ void dml_init_instance(struct display_mode_lib *lib,
lib->soc = *soc_bb;
lib->ip = *ip_params;
lib->project = project;
switch (project) {
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
case DML_PROJECT_NAVI10:
lib->funcs = dml20_funcs;
break;
#endif
default:
break;
}
}
const char *dml_get_status_message(enum dm_validation_status status)

29
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
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@ -27,18 +27,43 @@
#include "dml_common_defs.h"
#include "dml1_display_rq_dlg_calc.h"
#include "display_mode_vba.h"
enum dml_project {
DML_PROJECT_UNDEFINED,
DML_PROJECT_RAVEN1
DML_PROJECT_RAVEN1,
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
DML_PROJECT_NAVI10,
#endif
};
struct dml_funcs {
void (*rq_dlg_get_dlg_reg)(
struct display_mode_lib *mode_lib,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
const bool pstate_en);
void (*rq_dlg_get_rq_reg)(
struct display_mode_lib *mode_lib,
display_rq_regs_st *rq_regs,
const display_pipe_params_st pipe_param);
void (*recalculate)(struct display_mode_lib *mode_lib);
void (*validate)(struct display_mode_lib *mode_lib);
};
struct display_mode_lib {
struct _vcs_dpi_ip_params_st ip;
struct _vcs_dpi_soc_bounding_box_st soc;
enum dml_project project;
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
struct vba_vars_st vba;
#endif
struct dal_logger *logger;
struct dml_funcs funcs;
};
void dml_init_instance(struct display_mode_lib *lib,

26
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
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@ -57,6 +57,7 @@ struct _vcs_dpi_voltage_scaling_st {
double dscclk_mhz;
double dcfclk_mhz;
double socclk_mhz;
double phyclk_d18_mhz;
double dram_speed_mts;
double fabricclk_mhz;
double dispclk_mhz;
@ -97,6 +98,7 @@ struct _vcs_dpi_soc_bounding_box_st {
unsigned int num_banks;
unsigned int num_chans;
unsigned int vmm_page_size_bytes;
unsigned int hostvm_min_page_size_bytes;
double dram_clock_change_latency_us;
double writeback_dram_clock_change_latency_us;
unsigned int return_bus_width_bytes;
@ -135,6 +137,21 @@ struct _vcs_dpi_ip_params_st {
unsigned int writeback_luma_buffer_size_kbytes;
unsigned int writeback_chroma_buffer_size_kbytes;
unsigned int writeback_chroma_line_buffer_width_pixels;
unsigned int writeback_interface_buffer_size_kbytes;
unsigned int writeback_line_buffer_buffer_size;
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
unsigned int writeback_10bpc420_supported;
double writeback_max_hscl_ratio;
double writeback_max_vscl_ratio;
double writeback_min_hscl_ratio;
double writeback_min_vscl_ratio;
unsigned int writeback_max_hscl_taps;
unsigned int writeback_max_vscl_taps;
unsigned int writeback_line_buffer_luma_buffer_size;
unsigned int writeback_line_buffer_chroma_buffer_size;
#endif
unsigned int max_page_table_levels;
unsigned int max_num_dpp;
unsigned int max_num_otg;
@ -152,6 +169,13 @@ struct _vcs_dpi_ip_params_st {
unsigned int max_hscl_taps;
unsigned int max_vscl_taps;
unsigned int xfc_supported;
unsigned int ptoi_supported;
unsigned int gfx7_compat_tiling_supported;
bool odm_combine_4to1_supported;
bool dynamic_metadata_vm_enabled;
unsigned int max_num_hdmi_frl_outputs;
unsigned int xfc_fill_constant_bytes;
double dispclk_ramp_margin_percent;
double xfc_fill_bw_overhead_percent;
@ -218,6 +242,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
unsigned int hsplit_grp;
unsigned char xfc_enable;
unsigned char xfc_slave;
unsigned char immediate_flip;
struct _vcs_dpi_display_xfc_params_st xfc_params;
//for vstartuplines calculation freesync
unsigned char v_total_min;
@ -225,6 +250,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
};
struct writeback_st {
int wb_src_height;
int wb_src_width;
int wb_dst_width;
int wb_dst_height;
int wb_pixel_format;

845
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c Normal file
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@ -0,0 +1,845 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
#include "display_mode_lib.h"
#include "display_mode_vba.h"
#include "dml_inline_defs.h"
/*
* NOTE:
* This file is gcc-parsable HW gospel, coming straight from HW engineers.
*
* It doesn't adhere to Linux kernel style and sometimes will do things in odd
* ways. Unless there is something clearly wrong with it the code should
* remain as-is as it provides us with a guarantee from HW that it is correct.
*/
static void fetch_socbb_params(struct display_mode_lib *mode_lib);
static void fetch_ip_params(struct display_mode_lib *mode_lib);
static void fetch_pipe_params(struct display_mode_lib *mode_lib);
static void recalculate_params(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
static unsigned int CursorBppEnumToBits(enum cursor_bpp ebpp);
unsigned int dml_get_voltage_level(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes)
{
bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0
|| memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0
|| num_pipes != mode_lib->vba.cache_num_pipes
|| memcmp(pipes, mode_lib->vba.cache_pipes,
sizeof(display_e2e_pipe_params_st) * num_pipes) != 0;
mode_lib->vba.soc = mode_lib->soc;
mode_lib->vba.ip = mode_lib->ip;
memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes);
mode_lib->vba.cache_num_pipes = num_pipes;
if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0)
mode_lib->funcs.recalculate(mode_lib);
else {
fetch_socbb_params(mode_lib);
fetch_ip_params(mode_lib);
fetch_pipe_params(mode_lib);
PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
}
mode_lib->funcs.validate(mode_lib);
/* check if Mode Support Validation failed */
if (mode_lib->vba.VoltageLevel > mode_lib->vba.soc.num_states) {
/* get the validation status for highest voltage level and output console message */
enum dm_validation_status status = mode_lib->vba.ValidationStatus[mode_lib->vba.soc.num_states];
if (status != DML_FAIL_PITCH_SUPPORT) {
/*AlignedYPitch is based on swizzle mode, so it is normal if some swizzle mode not supported*/
dm_output_to_console("Mode Validation Error: %s failed validation.\n", dml_get_status_message(status));
}
}
return mode_lib->vba.VoltageLevel;
}
#define dml_get_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) \
{ \
recalculate_params(mode_lib, pipes, num_pipes); \
return var; \
}
dml_get_attr_func(clk_dcf_deepsleep, mode_lib->vba.DCFCLKDeepSleep);
dml_get_attr_func(wm_urgent, mode_lib->vba.UrgentWatermark);
dml_get_attr_func(wm_memory_trip, mode_lib->vba.UrgentLatency);
dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark);
dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark);
dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark);
dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark);
dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark);
dml_get_attr_func(wm_xfc_underflow, mode_lib->vba.UrgentWatermark); // xfc_underflow maps to urgent
dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency);
dml_get_attr_func(stutter_efficiency_no_vblank, mode_lib->vba.StutterEfficiencyNotIncludingVBlank);
dml_get_attr_func(urgent_latency, mode_lib->vba.UrgentLatency);
dml_get_attr_func(urgent_extra_latency, mode_lib->vba.UrgentExtraLatency);
dml_get_attr_func(nonurgent_latency, mode_lib->vba.NonUrgentLatencyTolerance);
dml_get_attr_func(
dram_clock_change_latency,
mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
dml_get_attr_func(dispclk_calculated, mode_lib->vba.DISPCLK_calculated);
dml_get_attr_func(total_data_read_bw, mode_lib->vba.TotalDataReadBandwidth);
dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth);
dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
#define dml_get_pipe_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
{\
unsigned int which_plane; \
recalculate_params(mode_lib, pipes, num_pipes); \
which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
return var[which_plane]; \
}
dml_get_pipe_attr_func(dsc_delay, mode_lib->vba.DSCDelay);
dml_get_pipe_attr_func(dppclk_calculated, mode_lib->vba.DPPCLK_calculated);
dml_get_pipe_attr_func(dscclk_calculated, mode_lib->vba.DSCCLK_calculated);
dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
dml_get_pipe_attr_func(vratio_prefetch_l, mode_lib->vba.VRatioPrefetchY);
dml_get_pipe_attr_func(vratio_prefetch_c, mode_lib->vba.VRatioPrefetchC);
dml_get_pipe_attr_func(dst_x_after_scaler, mode_lib->vba.DSTXAfterScaler);
dml_get_pipe_attr_func(dst_y_after_scaler, mode_lib->vba.DSTYAfterScaler);
dml_get_pipe_attr_func(dst_y_per_vm_vblank, mode_lib->vba.DestinationLinesToRequestVMInVBlank);
dml_get_pipe_attr_func(dst_y_per_row_vblank, mode_lib->vba.DestinationLinesToRequestRowInVBlank);
dml_get_pipe_attr_func(dst_y_prefetch, mode_lib->vba.DestinationLinesForPrefetch);
dml_get_pipe_attr_func(dst_y_per_vm_flip, mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip);
dml_get_pipe_attr_func(
dst_y_per_row_flip,
mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip);
dml_get_pipe_attr_func(xfc_transfer_delay, mode_lib->vba.XFCTransferDelay);
dml_get_pipe_attr_func(xfc_precharge_delay, mode_lib->vba.XFCPrechargeDelay);
dml_get_pipe_attr_func(xfc_remote_surface_flip_latency, mode_lib->vba.XFCRemoteSurfaceFlipLatency);
dml_get_pipe_attr_func(xfc_prefetch_margin, mode_lib->vba.XFCPrefetchMargin);
dml_get_pipe_attr_func(refcyc_per_vm_group_vblank, mode_lib->vba.TimePerVMGroupVBlank);
dml_get_pipe_attr_func(refcyc_per_vm_group_flip, mode_lib->vba.TimePerVMGroupFlip);
dml_get_pipe_attr_func(refcyc_per_vm_req_vblank, mode_lib->vba.TimePerVMRequestVBlank);
dml_get_pipe_attr_func(refcyc_per_vm_req_flip, mode_lib->vba.TimePerVMRequestFlip);
unsigned int get_vstartup_calculated(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes,
unsigned int which_pipe)
{
unsigned int which_plane;
recalculate_params(mode_lib, pipes, num_pipes);
which_plane = mode_lib->vba.pipe_plane[which_pipe];
return mode_lib->vba.VStartup[which_plane];
}
double get_total_immediate_flip_bytes(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes)
{
recalculate_params(mode_lib, pipes, num_pipes);
return mode_lib->vba.TotImmediateFlipBytes;
}
double get_total_immediate_flip_bw(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes)
{
unsigned int k;
double immediate_flip_bw = 0.0;
recalculate_params(mode_lib, pipes, num_pipes);
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
immediate_flip_bw += mode_lib->vba.ImmediateFlipBW[k];
return immediate_flip_bw;
}
double get_total_prefetch_bw(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes)
{
unsigned int k;
double total_prefetch_bw = 0.0;
recalculate_params(mode_lib, pipes, num_pipes);
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
total_prefetch_bw += mode_lib->vba.PrefetchBandwidth[k];
return total_prefetch_bw;
}
static void fetch_socbb_params(struct display_mode_lib *mode_lib)
{
soc_bounding_box_st *soc = &mode_lib->vba.soc;
int i;
// SOC Bounding Box Parameters
mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes;
mode_lib->vba.NumberOfChannels = soc->num_chans;
mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly =
soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // there's always that one bastard variable that's so long it throws everything out of alignment!
mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData =
soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly =
soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation =
soc->max_avg_sdp_bw_use_normal_percent;
mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation =
soc->max_avg_dram_bw_use_normal_percent;
mode_lib->vba.UrgentLatencyPixelDataOnly = soc->urgent_latency_pixel_data_only_us;
mode_lib->vba.UrgentLatencyPixelMixedWithVMData = soc->urgent_latency_pixel_mixed_with_vm_data_us;
mode_lib->vba.UrgentLatencyVMDataOnly = soc->urgent_latency_vm_data_only_us;
mode_lib->vba.RoundTripPingLatencyCycles = soc->round_trip_ping_latency_dcfclk_cycles;
mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly =
soc->urgent_out_of_order_return_per_channel_pixel_only_bytes;
mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData =
soc->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly =
soc->urgent_out_of_order_return_per_channel_vm_only_bytes;
mode_lib->vba.WritebackLatency = soc->writeback_latency_us;
mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
mode_lib->vba.Downspreading = soc->downspread_percent;
mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new!
mode_lib->vba.FabricDatapathToDCNDataReturn = soc->fabric_datapath_to_dcn_data_return_bytes; // new!
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading = soc->dcn_downspread_percent; // new
mode_lib->vba.DISPCLKDPPCLKVCOSpeed = soc->dispclk_dppclk_vco_speed_mhz; // new
mode_lib->vba.VMMPageSize = soc->vmm_page_size_bytes;
mode_lib->vba.GPUVMMinPageSize = soc->vmm_page_size_bytes / 1024;
mode_lib->vba.HostVMMinPageSize = soc->hostvm_min_page_size_bytes / 1024;
// Set the voltage scaling clocks as the defaults. Most of these will
// be set to different values by the test
for (i = 0; i < mode_lib->vba.soc.num_states; i++)
if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel)
break;
mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz;
mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz;
mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts;
mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz;
mode_lib->vba.XFCBusTransportTime = soc->xfc_bus_transport_time_us;
mode_lib->vba.XFCXBUFLatencyTolerance = soc->xfc_xbuf_latency_tolerance_us;
mode_lib->vba.UseUrgentBurstBandwidth = soc->use_urgent_burst_bw;
mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp = false;
mode_lib->vba.WritebackLumaAndChromaScalingSupported = true;
mode_lib->vba.MaxHSCLRatio = 4;
mode_lib->vba.MaxVSCLRatio = 4;
mode_lib->vba.Cursor64BppSupport = true;
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz;
mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz;
mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz;
mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz;
mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz;
mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts;
//mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz;
mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
}
}
static void fetch_ip_params(struct display_mode_lib *mode_lib)
{
ip_params_st *ip = &mode_lib->vba.ip;
// IP Parameters
mode_lib->vba.MaxNumDPP = ip->max_num_dpp;
mode_lib->vba.MaxNumOTG = ip->max_num_otg;
mode_lib->vba.MaxNumHDMIFRLOutputs = ip->max_num_hdmi_frl_outputs;
mode_lib->vba.MaxNumWriteback = ip->max_num_wb;
mode_lib->vba.CursorChunkSize = ip->cursor_chunk_size;
mode_lib->vba.CursorBufferSize = ip->cursor_buffer_size;
mode_lib->vba.MaxDCHUBToPSCLThroughput = ip->max_dchub_pscl_bw_pix_per_clk;
mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk;
mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes;
mode_lib->vba.DETBufferSizeInKByte = ip->det_buffer_size_kbytes;
mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
mode_lib->vba.WritebackChunkSize = ip->writeback_chunk_size_kbytes;
mode_lib->vba.LineBufferSize = ip->line_buffer_size_bits;
mode_lib->vba.MaxLineBufferLines = ip->max_line_buffer_lines;
mode_lib->vba.PTEBufferSizeInRequestsLuma = ip->dpte_buffer_size_in_pte_reqs_luma;
mode_lib->vba.PTEBufferSizeInRequestsChroma = ip->dpte_buffer_size_in_pte_reqs_chroma;
mode_lib->vba.DPPOutputBufferPixels = ip->dpp_output_buffer_pixels;
mode_lib->vba.OPPOutputBufferLines = ip->opp_output_buffer_lines;
mode_lib->vba.MaxHSCLRatio = ip->max_hscl_ratio;
mode_lib->vba.MaxVSCLRatio = ip->max_vscl_ratio;
mode_lib->vba.WritebackInterfaceLumaBufferSize = ip->writeback_luma_buffer_size_kbytes * 1024;
mode_lib->vba.WritebackInterfaceChromaBufferSize = ip->writeback_chroma_buffer_size_kbytes * 1024;
mode_lib->vba.WritebackInterfaceBufferSize = ip->writeback_interface_buffer_size_kbytes;
mode_lib->vba.WritebackLineBufferSize = ip->writeback_line_buffer_buffer_size;
mode_lib->vba.WritebackSupportInterleaveAndUsingWholeBufferForASingleStream = false;
mode_lib->vba.MinVoltageLevel = 0;
mode_lib->vba.MaxVoltageLevel = 5;
mode_lib->vba.WritebackChromaLineBufferWidth =
ip->writeback_chroma_line_buffer_width_pixels;
mode_lib->vba.WritebackLineBufferLumaBufferSize =
ip->writeback_line_buffer_luma_buffer_size;
mode_lib->vba.WritebackLineBufferChromaBufferSize =
ip->writeback_line_buffer_chroma_buffer_size;
mode_lib->vba.Writeback10bpc420Supported = ip->writeback_10bpc420_supported;
mode_lib->vba.WritebackMaxHSCLRatio = ip->writeback_max_hscl_ratio;
mode_lib->vba.WritebackMaxVSCLRatio = ip->writeback_max_vscl_ratio;
mode_lib->vba.WritebackMinHSCLRatio = ip->writeback_min_hscl_ratio;
mode_lib->vba.WritebackMinVSCLRatio = ip->writeback_min_vscl_ratio;
mode_lib->vba.WritebackMaxHSCLTaps = ip->writeback_max_hscl_taps;
mode_lib->vba.WritebackMaxVSCLTaps = ip->writeback_max_vscl_taps;
mode_lib->vba.GPUVMMaxPageTableLevels = ip->gpuvm_max_page_table_levels;
mode_lib->vba.HostVMMaxNonCachedPageTableLevels = ip->hostvm_max_page_table_levels;
mode_lib->vba.HostVMMaxPageTableLevels = ip->hostvm_max_page_table_levels;
mode_lib->vba.HostVMCachedPageTableLevels = ip->hostvm_cached_page_table_levels;
mode_lib->vba.MaxInterDCNTileRepeaters = ip->max_inter_dcn_tile_repeaters;
mode_lib->vba.NumberOfDSC = ip->num_dsc;
mode_lib->vba.ODMCapability = ip->odm_capable;
mode_lib->vba.DISPCLKRampingMargin = ip->dispclk_ramp_margin_percent;
mode_lib->vba.XFCSupported = ip->xfc_supported;
mode_lib->vba.XFCFillBWOverhead = ip->xfc_fill_bw_overhead_percent;
mode_lib->vba.XFCFillConstant = ip->xfc_fill_constant_bytes;
mode_lib->vba.DPPCLKDelaySubtotal = ip->dppclk_delay_subtotal;
mode_lib->vba.DPPCLKDelaySCL = ip->dppclk_delay_scl;
mode_lib->vba.DPPCLKDelaySCLLBOnly = ip->dppclk_delay_scl_lb_only;
mode_lib->vba.DPPCLKDelayCNVCFormater = ip->dppclk_delay_cnvc_formatter;
mode_lib->vba.DPPCLKDelayCNVCCursor = ip->dppclk_delay_cnvc_cursor;
mode_lib->vba.DISPCLKDelaySubtotal = ip->dispclk_delay_subtotal;
mode_lib->vba.DynamicMetadataVMEnabled = ip->dynamic_metadata_vm_enabled;
mode_lib->vba.ODMCombine4To1Supported = ip->odm_combine_4to1_supported;
mode_lib->vba.ProgressiveToInterlaceUnitInOPP = ip->ptoi_supported;
mode_lib->vba.PDEProcessingBufIn64KBReqs = ip->pde_proc_buffer_size_64k_reqs;
mode_lib->vba.PTEGroupSize = ip->pte_group_size_bytes;
mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp = ip->gfx7_compat_tiling_supported;
}
static void fetch_pipe_params(struct display_mode_lib *mode_lib)
{
display_e2e_pipe_params_st *pipes = mode_lib->vba.cache_pipes;
ip_params_st *ip = &mode_lib->vba.ip;
unsigned int OTGInstPlane[DC__NUM_DPP__MAX];
unsigned int j, k;
bool PlaneVisited[DC__NUM_DPP__MAX];
bool visited[DC__NUM_DPP__MAX];
// Convert Pipes to Planes
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k)
visited[k] = false;
mode_lib->vba.NumberOfActivePlanes = 0;
for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {
display_pipe_source_params_st *src = &pipes[j].pipe.src;
display_pipe_dest_params_st *dst = &pipes[j].pipe.dest;
scaler_ratio_depth_st *scl = &pipes[j].pipe.scale_ratio_depth;
scaler_taps_st *taps = &pipes[j].pipe.scale_taps;
display_output_params_st *dout = &pipes[j].dout;
display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg;
if (visited[j])
continue;
visited[j] = true;
mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
(enum scan_direction_class) (src->source_scan);
mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_width;
mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_width_c;
mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_height;
mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_height_c;
mode_lib->vba.ViewportYStartY[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_y_y;
mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] =
src->viewport_y_c;
mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height;
mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c;
mode_lib->vba.SurfaceHeightC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_c;
mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch;
mode_lib->vba.DCCMetaPitchC[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch_c;
mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
mode_lib->vba.HRatioChroma[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio_c;
mode_lib->vba.VRatio[mode_lib->vba.NumberOfActivePlanes] = scl->vscl_ratio;
mode_lib->vba.VRatioChroma[mode_lib->vba.NumberOfActivePlanes] = scl->vscl_ratio_c;
mode_lib->vba.ScalerEnabled[mode_lib->vba.NumberOfActivePlanes] = scl->scl_enable;
mode_lib->vba.Interlace[mode_lib->vba.NumberOfActivePlanes] = dst->interlaced;
if (dst->interlaced && !ip->ptoi_supported) {
mode_lib->vba.VRatio[mode_lib->vba.NumberOfActivePlanes] *= 2.0;
mode_lib->vba.VRatioChroma[mode_lib->vba.NumberOfActivePlanes] *= 2.0;
}
mode_lib->vba.htaps[mode_lib->vba.NumberOfActivePlanes] = taps->htaps;
mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps;
mode_lib->vba.HTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->htaps_c;
mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal;
mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal;
mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] =
src->dcc_use_global ?
ip->dcc_supported : src->dcc && ip->dcc_supported;
mode_lib->vba.DCCRate[mode_lib->vba.NumberOfActivePlanes] = src->dcc_rate;
/* TODO: Needs to be set based on src->dcc_rate_luma/chroma */
mode_lib->vba.DCCRateLuma[mode_lib->vba.NumberOfActivePlanes] = 0;
mode_lib->vba.DCCRateChroma[mode_lib->vba.NumberOfActivePlanes] = 0;
mode_lib->vba.SourcePixelFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum source_format_class) (src->source_format);
mode_lib->vba.HActive[mode_lib->vba.NumberOfActivePlanes] = dst->hactive;
mode_lib->vba.VActive[mode_lib->vba.NumberOfActivePlanes] = dst->vactive;
mode_lib->vba.SurfaceTiling[mode_lib->vba.NumberOfActivePlanes] =
(enum dm_swizzle_mode) (src->sw_mode);
mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] =
dst->recout_width; // TODO: or should this be full_recout_width???...maybe only when in hsplit mode?
mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
dst->odm_combine;
mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum output_format_class) (dout->output_format);
mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] =
(enum output_encoder_class) (dout->output_type);
mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] = dout->output_bpp;
mode_lib->vba.OutputLinkDPLanes[mode_lib->vba.NumberOfActivePlanes] =
dout->dp_lanes;
/* TODO: Needs to be set based on dout->audio.audio_sample_rate_khz/sample_layout */
mode_lib->vba.AudioSampleRate[mode_lib->vba.NumberOfActivePlanes] =
44.1 * 1000;
mode_lib->vba.AudioSampleLayout[mode_lib->vba.NumberOfActivePlanes] =
1;
mode_lib->vba.DRAMClockChangeLatencyOverride = 0.0;
mode_lib->vba.DSCEnabled[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable;
mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] =
dout->dsc_slices;
mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
dout->output_bpc == 0 ? 12 : dout->output_bpc;
mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = dout->wb_enable;
mode_lib->vba.ActiveWritebacksPerPlane[mode_lib->vba.NumberOfActivePlanes] =
dout->num_active_wb;
mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_src_height;
mode_lib->vba.WritebackSourceWidth[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_src_width;
mode_lib->vba.WritebackDestinationWidth[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_dst_width;
mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_dst_height;
mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum source_format_class) (dout->wb.wb_pixel_format);
mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_htaps_luma;
mode_lib->vba.WritebackVTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_vtaps_luma;
mode_lib->vba.WritebackLumaHTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_htaps_luma;
mode_lib->vba.WritebackLumaVTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_vtaps_luma;
mode_lib->vba.WritebackChromaHTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_htaps_chroma;
mode_lib->vba.WritebackChromaVTaps[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_vtaps_chroma;
mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_hratio;
mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_vratio;
mode_lib->vba.DynamicMetadataEnable[mode_lib->vba.NumberOfActivePlanes] =
src->dynamic_metadata_enable;
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[mode_lib->vba.NumberOfActivePlanes] =
src->dynamic_metadata_lines_before_active;
mode_lib->vba.DynamicMetadataTransmittedBytes[mode_lib->vba.NumberOfActivePlanes] =
src->dynamic_metadata_xmit_bytes;
mode_lib->vba.XFCEnabled[mode_lib->vba.NumberOfActivePlanes] = src->xfc_enable
&& ip->xfc_supported;
mode_lib->vba.XFCSlvChunkSize = src->xfc_params.xfc_slv_chunk_size_bytes;
mode_lib->vba.XFCTSlvVupdateOffset = src->xfc_params.xfc_tslv_vupdate_offset_us;
mode_lib->vba.XFCTSlvVupdateWidth = src->xfc_params.xfc_tslv_vupdate_width_us;
mode_lib->vba.XFCTSlvVreadyOffset = src->xfc_params.xfc_tslv_vready_offset_us;
mode_lib->vba.PixelClock[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz;
mode_lib->vba.PixelClockBackEnd[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz;
mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz;
if (ip->is_line_buffer_bpp_fixed)
mode_lib->vba.LBBitPerPixel[mode_lib->vba.NumberOfActivePlanes] =
ip->line_buffer_fixed_bpp;
else {
unsigned int lb_depth;
switch (scl->lb_depth) {
case dm_lb_6:
lb_depth = 18;
break;
case dm_lb_8:
lb_depth = 24;
break;
case dm_lb_10:
lb_depth = 30;
break;
case dm_lb_12:
lb_depth = 36;
break;
case dm_lb_16:
lb_depth = 48;
break;
default:
lb_depth = 36;
}
mode_lib->vba.LBBitPerPixel[mode_lib->vba.NumberOfActivePlanes] = lb_depth;
}
mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes] = 0;
// The DML spreadsheet assumes that the two cursors utilize the same amount of bandwidth. We'll
// calculate things a little more accurately
for (k = 0; k < DC__NUM_CURSOR__MAX; ++k) {
switch (k) {
case 0:
mode_lib->vba.CursorBPP[mode_lib->vba.NumberOfActivePlanes][0] =
CursorBppEnumToBits(
(enum cursor_bpp) (src->cur0_bpp));
mode_lib->vba.CursorWidth[mode_lib->vba.NumberOfActivePlanes][0] =
src->cur0_src_width;
if (src->cur0_src_width > 0)
mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes]++;
break;
case 1:
mode_lib->vba.CursorBPP[mode_lib->vba.NumberOfActivePlanes][1] =
CursorBppEnumToBits(
(enum cursor_bpp) (src->cur1_bpp));
mode_lib->vba.CursorWidth[mode_lib->vba.NumberOfActivePlanes][1] =
src->cur1_src_width;
if (src->cur1_src_width > 0)
mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes]++;
break;
default:
dml_print(
"ERROR: Number of cursors specified exceeds supported maximum\n")
;
}
}
OTGInstPlane[mode_lib->vba.NumberOfActivePlanes] = dst->otg_inst;
if (j == 0)
mode_lib->vba.UseMaximumVStartup = dst->use_maximum_vstartup;
else
mode_lib->vba.UseMaximumVStartup = mode_lib->vba.UseMaximumVStartup
|| dst->use_maximum_vstartup;
if (dst->odm_combine && !src->is_hsplit)
dml_print(
"ERROR: ODM Combine is specified but is_hsplit has not be specified for pipe %i\n",
j);
if (src->is_hsplit) {
for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
display_output_params_st *dout_k = &pipes[k].dout;
if (src_k->is_hsplit && !visited[k]
&& src->hsplit_grp == src_k->hsplit_grp) {
mode_lib->vba.pipe_plane[k] =
mode_lib->vba.NumberOfActivePlanes;
mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes]++;
if (mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes]
== dm_horz)
mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=
src_k->viewport_width;
else
mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
src_k->viewport_height;
mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] +=
dout_k->dsc_slices;
visited[k] = true;
}
}
}
if (pipes[k].pipe.src.immediate_flip)
mode_lib->vba.ImmediateFlipSupport = true;
mode_lib->vba.NumberOfActivePlanes++;
}
// handle overlays through BlendingAndTiming
// BlendingAndTiming tells you which instance to look at to get timing, the so called 'master'
for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
PlaneVisited[j] = false;
for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
for (k = j + 1; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if (!PlaneVisited[k] && OTGInstPlane[j] == OTGInstPlane[k]) {
// doesn't matter, so choose the smaller one
mode_lib->vba.BlendingAndTiming[j] = j;
PlaneVisited[j] = true;
mode_lib->vba.BlendingAndTiming[k] = j;
PlaneVisited[k] = true;
}
}
if (!PlaneVisited[j]) {
mode_lib->vba.BlendingAndTiming[j] = j;
PlaneVisited[j] = true;
}
}
// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified
// Do we want the dscclk to automatically be halved? Guess not since the value is specified
mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k)
ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
mode_lib->vba.GPUVMEnable = false;
mode_lib->vba.HostVMEnable = false;
mode_lib->vba.OverrideGPUVMPageTableLevels = 0;
mode_lib->vba.OverrideHostVMPageTableLevels = 0;
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].pipe.src.vm;
mode_lib->vba.OverrideGPUVMPageTableLevels =
(pipes[k].pipe.src.gpuvm_levels_force_en
&& mode_lib->vba.OverrideGPUVMPageTableLevels
< pipes[k].pipe.src.gpuvm_levels_force) ?
pipes[k].pipe.src.gpuvm_levels_force :
mode_lib->vba.OverrideGPUVMPageTableLevels;
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable || !!pipes[k].pipe.src.hostvm || !!pipes[k].pipe.src.vm;
mode_lib->vba.OverrideHostVMPageTableLevels =
(pipes[k].pipe.src.hostvm_levels_force_en
&& mode_lib->vba.OverrideHostVMPageTableLevels
< pipes[k].pipe.src.hostvm_levels_force) ?
pipes[k].pipe.src.hostvm_levels_force :
mode_lib->vba.OverrideHostVMPageTableLevels;
}
mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank = dm_try_to_allow_self_refresh_and_mclk_switch;
if (mode_lib->vba.OverrideGPUVMPageTableLevels)
mode_lib->vba.GPUVMMaxPageTableLevels = mode_lib->vba.OverrideGPUVMPageTableLevels;
if (mode_lib->vba.OverrideHostVMPageTableLevels)
mode_lib->vba.HostVMMaxPageTableLevels = mode_lib->vba.OverrideHostVMPageTableLevels;
mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable && !!ip->gpuvm_enable;
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && !!ip->hostvm_enable;
}
// in wm mode we pull the parameters needed from the display_e2e_pipe_params_st structs
// rather than working them out as in recalculate_ms
static void recalculate_params(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes)
{
// This is only safe to use memcmp because there are non-POD types in struct display_mode_lib
if (memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0
|| memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0
|| num_pipes != mode_lib->vba.cache_num_pipes
|| memcmp(
pipes,
mode_lib->vba.cache_pipes,
sizeof(display_e2e_pipe_params_st) * num_pipes) != 0) {
mode_lib->vba.soc = mode_lib->soc;
mode_lib->vba.ip = mode_lib->ip;
memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes);
mode_lib->vba.cache_num_pipes = num_pipes;
mode_lib->funcs.recalculate(mode_lib);
}
}
bool Calculate256BBlockSizes(
enum source_format_class SourcePixelFormat,
enum dm_swizzle_mode SurfaceTiling,
unsigned int BytePerPixelY,
unsigned int BytePerPixelC,
unsigned int *BlockHeight256BytesY,
unsigned int *BlockHeight256BytesC,
unsigned int *BlockWidth256BytesY,
unsigned int *BlockWidth256BytesC)
{
if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32
|| SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8)) {
if (SurfaceTiling == dm_sw_linear) {
*BlockHeight256BytesY = 1;
} else if (SourcePixelFormat == dm_444_64) {
*BlockHeight256BytesY = 4;
} else if (SourcePixelFormat == dm_444_8) {
*BlockHeight256BytesY = 16;
} else {
*BlockHeight256BytesY = 8;
}
*BlockWidth256BytesY = 256 / BytePerPixelY / *BlockHeight256BytesY;
*BlockHeight256BytesC = 0;
*BlockWidth256BytesC = 0;
} else {
if (SurfaceTiling == dm_sw_linear) {
*BlockHeight256BytesY = 1;
*BlockHeight256BytesC = 1;
} else if (SourcePixelFormat == dm_420_8) {
*BlockHeight256BytesY = 16;
*BlockHeight256BytesC = 8;
} else {
*BlockHeight256BytesY = 8;
*BlockHeight256BytesC = 8;
}
*BlockWidth256BytesY = 256 / BytePerPixelY / *BlockHeight256BytesY;
*BlockWidth256BytesC = 256 / BytePerPixelC / *BlockHeight256BytesC;
}
return true;
}
bool CalculateMinAndMaxPrefetchMode(
enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
unsigned int *MinPrefetchMode,
unsigned int *MaxPrefetchMode)
{
if (AllowDRAMSelfRefreshOrDRAMClockChangeInVblank
== dm_neither_self_refresh_nor_mclk_switch) {
*MinPrefetchMode = 2;
*MaxPrefetchMode = 2;
return false;
} else if (AllowDRAMSelfRefreshOrDRAMClockChangeInVblank == dm_allow_self_refresh) {
*MinPrefetchMode = 1;
*MaxPrefetchMode = 1;
return false;
} else if (AllowDRAMSelfRefreshOrDRAMClockChangeInVblank
== dm_allow_self_refresh_and_mclk_switch) {
*MinPrefetchMode = 0;
*MaxPrefetchMode = 0;
return false;
} else if (AllowDRAMSelfRefreshOrDRAMClockChangeInVblank
== dm_try_to_allow_self_refresh_and_mclk_switch) {
*MinPrefetchMode = 0;
*MaxPrefetchMode = 2;
return false;
}
*MinPrefetchMode = 0;
*MaxPrefetchMode = 2;
return true;
}
void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib)
{
unsigned int k;
//Progressive To Interlace Unit Effect
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
if (mode_lib->vba.Interlace[k] == 1
&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true) {
mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClockBackEnd[k];
}
}
}
static unsigned int CursorBppEnumToBits(enum cursor_bpp ebpp)
{
switch (ebpp) {
case dm_cur_2bit:
return 2;
case dm_cur_32bit:
return 32;
case dm_cur_64bit:
return 64;
default:
return 0;
}
}
void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
{
soc_bounding_box_st *soc = &mode_lib->vba.soc;
unsigned int k;
unsigned int total_pipes = 0;
mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel];
mode_lib->vba.FabricAndDRAMBandwidth = mode_lib->vba.FabricAndDRAMBandwidthPerState[mode_lib->vba.VoltageLevel];
fetch_socbb_params(mode_lib);
fetch_ip_params(mode_lib);
fetch_pipe_params(mode_lib);
mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz;
if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0)
mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz;
else
mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz;
// Total Available Pipes Support Check
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
total_pipes += mode_lib->vba.DPPPerPlane[k];
ASSERT(total_pipes <= DC__NUM_DPP__MAX);
}
double CalculateWriteBackDISPCLK(
enum source_format_class WritebackPixelFormat,
double PixelClock,
double WritebackHRatio,
double WritebackVRatio,
unsigned int WritebackLumaHTaps,
unsigned int WritebackLumaVTaps,
unsigned int WritebackChromaHTaps,
unsigned int WritebackChromaVTaps,
double WritebackDestinationWidth,
unsigned int HTotal,
unsigned int WritebackChromaLineBufferWidth)
{
double CalculateWriteBackDISPCLK = 1.01 * PixelClock * dml_max(
dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1)
* (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal,
dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal));
if (WritebackPixelFormat != dm_444_32) {
CalculateWriteBackDISPCLK = dml_max(CalculateWriteBackDISPCLK, 1.01 * PixelClock * dml_max(
dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio),
dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1)
+ dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal
+ dml_ceil(1 / (2 * WritebackVRatio), 1) * (dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal,
dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal)));
}
return CalculateWriteBackDISPCLK;
}
#endif

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drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h Normal file
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@ -0,0 +1,848 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML2_DISPLAY_MODE_VBA_H__
#define __DML2_DISPLAY_MODE_VBA_H__
#include "dml_common_defs.h"
struct display_mode_lib;
void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
dml_get_attr_decl(clk_dcf_deepsleep);
dml_get_attr_decl(wm_urgent);
dml_get_attr_decl(wm_memory_trip);
dml_get_attr_decl(wm_writeback_urgent);
dml_get_attr_decl(wm_stutter_exit);
dml_get_attr_decl(wm_stutter_enter_exit);
dml_get_attr_decl(wm_dram_clock_change);
dml_get_attr_decl(wm_writeback_dram_clock_change);
dml_get_attr_decl(wm_xfc_underflow);
dml_get_attr_decl(stutter_efficiency_no_vblank);
dml_get_attr_decl(stutter_efficiency);
dml_get_attr_decl(urgent_latency);
dml_get_attr_decl(urgent_extra_latency);
dml_get_attr_decl(nonurgent_latency);
dml_get_attr_decl(dram_clock_change_latency);
dml_get_attr_decl(dispclk_calculated);
dml_get_attr_decl(total_data_read_bw);
dml_get_attr_decl(return_bw);
dml_get_attr_decl(tcalc);
dml_get_attr_decl(fraction_of_urgent_bandwidth);
dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
dml_get_pipe_attr_decl(dsc_delay);
dml_get_pipe_attr_decl(dppclk_calculated);
dml_get_pipe_attr_decl(dscclk_calculated);
dml_get_pipe_attr_decl(min_ttu_vblank);
dml_get_pipe_attr_decl(vratio_prefetch_l);
dml_get_pipe_attr_decl(vratio_prefetch_c);
dml_get_pipe_attr_decl(dst_x_after_scaler);
dml_get_pipe_attr_decl(dst_y_after_scaler);
dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
dml_get_pipe_attr_decl(dst_y_per_row_vblank);
dml_get_pipe_attr_decl(dst_y_prefetch);
dml_get_pipe_attr_decl(dst_y_per_vm_flip);
dml_get_pipe_attr_decl(dst_y_per_row_flip);
dml_get_pipe_attr_decl(xfc_transfer_delay);
dml_get_pipe_attr_decl(xfc_precharge_delay);
dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
dml_get_pipe_attr_decl(xfc_prefetch_margin);
dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
unsigned int get_vstartup_calculated(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes,
unsigned int which_pipe);
double get_total_immediate_flip_bytes(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
double get_total_immediate_flip_bw(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
double get_total_prefetch_bw(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
unsigned int dml_get_voltage_level(
struct display_mode_lib *mode_lib,
const display_e2e_pipe_params_st *pipes,
unsigned int num_pipes);
void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
bool Calculate256BBlockSizes(
enum source_format_class SourcePixelFormat,
enum dm_swizzle_mode SurfaceTiling,
unsigned int BytePerPixelY,
unsigned int BytePerPixelC,
unsigned int *BlockHeight256BytesY,
unsigned int *BlockHeight256BytesC,
unsigned int *BlockWidth256BytesY,
unsigned int *BlockWidth256BytesC);
struct vba_vars_st {
ip_params_st ip;
soc_bounding_box_st soc;
int maxMpcComb;
bool UseMaximumVStartup;
double WritebackDISPCLK;
double DPPCLKUsingSingleDPPLuma;
double DPPCLKUsingSingleDPPChroma;
double DISPCLKWithRamping;
double DISPCLKWithoutRamping;
double GlobalDPPCLK;
double DISPCLKWithRampingRoundedToDFSGranularity;
double DISPCLKWithoutRampingRoundedToDFSGranularity;
double MaxDispclkRoundedToDFSGranularity;
bool DCCEnabledAnyPlane;
double ReturnBandwidthToDCN;
unsigned int TotalActiveDPP;
unsigned int TotalDCCActiveDPP;
double UrgentRoundTripAndOutOfOrderLatency;
double StutterPeriod;
double FrameTimeForMinFullDETBufferingTime;
double AverageReadBandwidth;
double TotalRowReadBandwidth;
double PartOfBurstThatFitsInROB;
double StutterBurstTime;
unsigned int NextPrefetchMode;
double NextMaxVStartup;
double VBlankTime;
double SmallestVBlank;
double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
double EffectiveDETPlusLBLinesLuma;
double EffectiveDETPlusLBLinesChroma;
double UrgentLatencySupportUsLuma;
double UrgentLatencySupportUsChroma;
unsigned int DSCFormatFactor;
bool PrefetchModeSupported;
enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
double XFCRemoteSurfaceFlipDelay;
double TInitXFill;
double TslvChk;
double SrcActiveDrainRate;
bool ImmediateFlipSupported;
enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
bool PrefetchERROR;
unsigned int VStartupLines;
unsigned int ActiveDPPs;
unsigned int LBLatencyHidingSourceLinesY;
unsigned int LBLatencyHidingSourceLinesC;
double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
double MinActiveDRAMClockChangeMargin;
double InitFillLevel;
double FinalFillMargin;
double FinalFillLevel;
double RemainingFillLevel;
double TFinalxFill;
//
// SOC Bounding Box Parameters
//
double SRExitTime;
double SREnterPlusExitTime;
double UrgentLatencyPixelDataOnly;
double UrgentLatencyPixelMixedWithVMData;
double UrgentLatencyVMDataOnly;
double UrgentLatency; // max of the above three
double WritebackLatency;
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
double NumberOfChannels;
double DRAMChannelWidth;
double FabricDatapathToDCNDataReturn;
double ReturnBusWidth;
double Downspreading;
double DISPCLKDPPCLKDSCCLKDownSpreading;
double DISPCLKDPPCLKVCOSpeed;
double RoundTripPingLatencyCycles;
double UrgentOutOfOrderReturnPerChannel;
double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
double UrgentOutOfOrderReturnPerChannelVMDataOnly;
unsigned int VMMPageSize;
double DRAMClockChangeLatency;
double XFCBusTransportTime;
bool UseUrgentBurstBandwidth;
double XFCXBUFLatencyTolerance;
//
// IP Parameters
//
unsigned int ROBBufferSizeInKByte;
double DETBufferSizeInKByte;
double DETBufferSizeInTime;
unsigned int DPPOutputBufferPixels;
unsigned int OPPOutputBufferLines;
unsigned int PixelChunkSizeInKByte;
double ReturnBW;
bool GPUVMEnable;
bool HostVMEnable;
unsigned int GPUVMMaxPageTableLevels;
unsigned int HostVMMaxPageTableLevels;
unsigned int HostVMCachedPageTableLevels;
unsigned int OverrideGPUVMPageTableLevels;
unsigned int OverrideHostVMPageTableLevels;
unsigned int MetaChunkSize;
double MinPixelChunkSizeBytes;
double MinMetaChunkSizeBytes;
unsigned int WritebackChunkSize;
bool ODMCapability;
unsigned int NumberOfDSC;
unsigned int LineBufferSize;
unsigned int MaxLineBufferLines;
unsigned int WritebackInterfaceLumaBufferSize;
unsigned int WritebackInterfaceChromaBufferSize;
unsigned int WritebackChromaLineBufferWidth;
double MaxDCHUBToPSCLThroughput;
double MaxPSCLToLBThroughput;
unsigned int PTEBufferSizeInRequestsLuma;
unsigned int PTEBufferSizeInRequestsChroma;
double DISPCLKRampingMargin;
unsigned int MaxInterDCNTileRepeaters;
bool XFCSupported;
double XFCSlvChunkSize;
double XFCFillBWOverhead;
double XFCFillConstant;
double XFCTSlvVupdateOffset;
double XFCTSlvVupdateWidth;
double XFCTSlvVreadyOffset;
double DPPCLKDelaySubtotal;
double DPPCLKDelaySCL;
double DPPCLKDelaySCLLBOnly;
double DPPCLKDelayCNVCFormater;
double DPPCLKDelayCNVCCursor;
double DISPCLKDelaySubtotal;
bool ProgressiveToInterlaceUnitInOPP;
// Pipe/Plane Parameters
int VoltageLevel;
double FabricClock;
double DRAMSpeed;
double DISPCLK;
double SOCCLK;
double DCFCLK;
unsigned int NumberOfActivePlanes;
unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
unsigned int ViewportWidth[DC__NUM_DPP__MAX];
unsigned int ViewportHeight[DC__NUM_DPP__MAX];
unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
unsigned int PitchY[DC__NUM_DPP__MAX];
unsigned int PitchC[DC__NUM_DPP__MAX];
double HRatio[DC__NUM_DPP__MAX];
double VRatio[DC__NUM_DPP__MAX];
unsigned int htaps[DC__NUM_DPP__MAX];
unsigned int vtaps[DC__NUM_DPP__MAX];
unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
unsigned int HTotal[DC__NUM_DPP__MAX];
unsigned int VTotal[DC__NUM_DPP__MAX];
int DPPPerPlane[DC__NUM_DPP__MAX];
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
bool DCCEnable[DC__NUM_DPP__MAX];
unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
bool WritebackEnable[DC__NUM_DPP__MAX];
unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
double WritebackDestinationWidth[DC__NUM_DPP__MAX];
double WritebackDestinationHeight[DC__NUM_DPP__MAX];
double WritebackSourceHeight[DC__NUM_DPP__MAX];
enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
double WritebackHRatio[DC__NUM_DPP__MAX];
double WritebackVRatio[DC__NUM_DPP__MAX];
unsigned int HActive[DC__NUM_DPP__MAX];
unsigned int VActive[DC__NUM_DPP__MAX];
bool Interlace[DC__NUM_DPP__MAX];
enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
double DCCRate[DC__NUM_DPP__MAX];
double AverageDCCCompressionRate;
bool ODMCombineEnabled[DC__NUM_DPP__MAX];
double OutputBpp[DC__NUM_DPP__MAX];
bool DSCEnabled[DC__NUM_DPP__MAX];
unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
enum output_encoder_class Output[DC__NUM_DPP__MAX];
unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
bool SynchronizedVBlank;
unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
bool XFCEnabled[DC__NUM_DPP__MAX];
bool ScalerEnabled[DC__NUM_DPP__MAX];
// Intermediates/Informational
bool ImmediateFlipSupport;
double DETBufferSizeY[DC__NUM_DPP__MAX];
double DETBufferSizeC[DC__NUM_DPP__MAX];
unsigned int SwathHeightY[DC__NUM_DPP__MAX];
unsigned int SwathHeightC[DC__NUM_DPP__MAX];
unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
double LastPixelOfLineExtraWatermark;
double TotalDataReadBandwidth;
unsigned int TotalActiveWriteback;
unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
double BandwidthAvailableForImmediateFlip;
unsigned int PrefetchMode[DC__VOLTAGE_STATES + 1][2];
unsigned int MinPrefetchMode;
unsigned int MaxPrefetchMode;
bool AnyLinesForVMOrRowTooLarge;
double MaxVStartup;
bool IgnoreViewportPositioning;
bool ErrorResult[DC__NUM_DPP__MAX];
//
// Calculated dml_ml->vba.Outputs
//
double DCFCLKDeepSleep;
double UrgentWatermark;
double UrgentExtraLatency;
double WritebackUrgentWatermark;
double StutterExitWatermark;
double StutterEnterPlusExitWatermark;
double DRAMClockChangeWatermark;
double WritebackDRAMClockChangeWatermark;
double StutterEfficiency;
double StutterEfficiencyNotIncludingVBlank;
double NonUrgentLatencyTolerance;
double MinActiveDRAMClockChangeLatencySupported;
// These are the clocks calcuated by the library but they are not actually
// used explicitly. They are fetched by tests and then possibly used. The
// ultimate values to use are the ones specified by the parameters to DML
double DISPCLK_calculated;
double DPPCLK_calculated[DC__NUM_DPP__MAX];
unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
double VUpdateWidthPix[DC__NUM_DPP__MAX];
double VReadyOffsetPix[DC__NUM_DPP__MAX];
unsigned int TotImmediateFlipBytes;
double TCalc;
display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
unsigned int cache_num_pipes;
unsigned int pipe_plane[DC__NUM_DPP__MAX];
/* vba mode support */
/*inputs*/
bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
double MaxHSCLRatio;
double MaxVSCLRatio;
unsigned int MaxNumWriteback;
bool WritebackLumaAndChromaScalingSupported;
bool Cursor64BppSupport;
double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
double FabricClockPerState[DC__VOLTAGE_STATES + 1];
double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
double MaxDppclk[DC__VOLTAGE_STATES + 1];
double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
double MaxDispclk[DC__VOLTAGE_STATES + 1];
int VoltageOverrideLevel;
/*outputs*/
bool ScaleRatioAndTapsSupport;
bool SourceFormatPixelAndScanSupport;
double TotalBandwidthConsumedGBytePerSecond;
bool DCCEnabledInAnyPlane;
bool WritebackLatencySupport;
bool WritebackModeSupport;
bool Writeback10bpc420Supported;
bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
unsigned int TotalNumberOfActiveWriteback;
double CriticalPoint;
double ReturnBWToDCNPerState;
bool IsErrorResult[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
bool prefetch_vm_bw_valid;
bool prefetch_row_bw_valid;
bool NumberOfOTGSupport;
bool NonsupportedDSCInputBPC;
bool WritebackScaleRatioAndTapsSupport;
bool CursorSupport;
bool PitchSupport;
enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES + 1];
double WritebackLineBufferLumaBufferSize;
double WritebackLineBufferChromaBufferSize;
double WritebackMinHSCLRatio;
double WritebackMinVSCLRatio;
double WritebackMaxHSCLRatio;
double WritebackMaxVSCLRatio;
double WritebackMaxHSCLTaps;
double WritebackMaxVSCLTaps;
unsigned int MaxNumDPP;
unsigned int MaxNumOTG;
double CursorBufferSize;
double CursorChunkSize;
unsigned int Mode;
double OutputLinkDPLanes[DC__NUM_DPP__MAX];
double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
double ImmediateFlipBW[DC__NUM_DPP__MAX];
double MaxMaxVStartup;
double WritebackLumaVExtra;
double WritebackChromaVExtra;
double WritebackRequiredDISPCLK;
double MaximumSwathWidthSupport;
double MaximumSwathWidthInDETBuffer;
double MaximumSwathWidthInLineBuffer;
double MaxDispclkRoundedDownToDFSGranularity;
double MaxDppclkRoundedDownToDFSGranularity;
double PlaneRequiredDISPCLKWithoutODMCombine;
double PlaneRequiredDISPCLKWithODMCombine;
double PlaneRequiredDISPCLK;
double TotalNumberOfActiveOTG;
double FECOverhead;
double EffectiveFECOverhead;
unsigned int Outbpp;
unsigned int OutbppDSC;
double TotalDSCUnitsRequired;
double bpp;
unsigned int slices;
double SwathWidthGranularityY;
double RoundedUpMaxSwathSizeBytesY;
double SwathWidthGranularityC;
double RoundedUpMaxSwathSizeBytesC;
double EffectiveDETLBLinesLuma;
double EffectiveDETLBLinesChroma;
double ProjectedDCFCLKDeepSleep;
double PDEAndMetaPTEBytesPerFrameY;
double PDEAndMetaPTEBytesPerFrameC;
unsigned int MetaRowBytesY;
unsigned int MetaRowBytesC;
unsigned int DPTEBytesPerRowC;
unsigned int DPTEBytesPerRowY;
double ExtraLatency;
double TimeCalc;
double TWait;
double MaximumReadBandwidthWithPrefetch;
double MaximumReadBandwidthWithoutPrefetch;
double total_dcn_read_bw_with_flip;
double total_dcn_read_bw_with_flip_no_urgent_burst;
double FractionOfUrgentBandwidth;
double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
/* ms locals */
double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES + 1];
unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
int NoOfDPPThisState[DC__NUM_DPP__MAX];
bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
double VRatioPreY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double VRatioPreC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES + 1];
bool PrefetchSupported[DC__VOLTAGE_STATES + 1][2];
bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
double RequiredDISPCLK[DC__VOLTAGE_STATES + 1][2];
bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1][2];
bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1][2];
unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1][2];
unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1][2];
bool ModeSupport[DC__VOLTAGE_STATES + 1][2];
double ReturnBWPerState[DC__VOLTAGE_STATES + 1];
bool DIOSupport[DC__VOLTAGE_STATES + 1];
bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
bool ROBSupport[DC__VOLTAGE_STATES + 1];
bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES + 1];
double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES + 1];
double PrefetchBW[DC__NUM_DPP__MAX];
double PDEAndMetaPTEBytesPerFrame[DC__NUM_DPP__MAX];
double MetaRowBytes[DC__NUM_DPP__MAX];
double DPTEBytesPerRow[DC__NUM_DPP__MAX];
double PrefetchLinesY[DC__NUM_DPP__MAX];
double PrefetchLinesC[DC__NUM_DPP__MAX];
unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
double PrefillY[DC__NUM_DPP__MAX];
double PrefillC[DC__NUM_DPP__MAX];
double LineTimesForPrefetch[DC__NUM_DPP__MAX];
double LinesForMetaPTE[DC__NUM_DPP__MAX];
double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
unsigned int SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
double BytePerPixelInDETY[DC__NUM_DPP__MAX];
double BytePerPixelInDETC[DC__NUM_DPP__MAX];
bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
double MaxSwathHeightY[DC__NUM_DPP__MAX];
double MaxSwathHeightC[DC__NUM_DPP__MAX];
double MinSwathHeightY[DC__NUM_DPP__MAX];
double MinSwathHeightC[DC__NUM_DPP__MAX];
double ReadBandwidthLuma[DC__NUM_DPP__MAX];
double ReadBandwidthChroma[DC__NUM_DPP__MAX];
double ReadBandwidth[DC__NUM_DPP__MAX];
double WriteBandwidth[DC__NUM_DPP__MAX];
double PSCL_FACTOR[DC__NUM_DPP__MAX];
double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
double MaximumVStartup[DC__NUM_DPP__MAX];
unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
double AlignedYPitch[DC__NUM_DPP__MAX];
double AlignedCPitch[DC__NUM_DPP__MAX];
double MaximumSwathWidth[DC__NUM_DPP__MAX];
double cursor_bw[DC__NUM_DPP__MAX];
double cursor_bw_pre[DC__NUM_DPP__MAX];
double Tno_bw[DC__NUM_DPP__MAX];
double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
double final_flip_bw[DC__NUM_DPP__MAX];
bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1][2];
double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
long dpte_group_bytes[DC__NUM_DPP__MAX];
unsigned int dpte_row_height[DC__NUM_DPP__MAX];
unsigned int meta_req_height[DC__NUM_DPP__MAX];
unsigned int meta_req_width[DC__NUM_DPP__MAX];
unsigned int meta_row_height[DC__NUM_DPP__MAX];
unsigned int meta_row_width[DC__NUM_DPP__MAX];
unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
double meta_row_bw[DC__NUM_DPP__MAX];
double dpte_row_bw[DC__NUM_DPP__MAX];
double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2];
double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
bool MPCCombine[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
double MaximumSwathWidthInLineBufferLuma;
double MaximumSwathWidthInLineBufferChroma;
double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
bool odm_combine_dummy[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
double dummy4[DC__NUM_DPP__MAX];
double dummy5;
double dummy6;
double dummy7[DC__NUM_DPP__MAX];
double dummy8[DC__NUM_DPP__MAX];
unsigned int dummyinteger1ms[DC__NUM_DPP__MAX];
unsigned int dummyinteger2ms[DC__NUM_DPP__MAX];
unsigned int dummyinteger3[DC__NUM_DPP__MAX];
unsigned int dummyinteger4;
unsigned int dummyinteger5;
unsigned int dummyinteger6;
unsigned int dummyinteger7;
unsigned int dummyinteger8;
unsigned int dummyinteger9;
unsigned int dummyinteger10;
unsigned int dummyinteger11;
unsigned int dummyinteger12;
bool dummysinglestring;
bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double PlaneRequiredDISPCLKWithODMCombine2To1;
double PlaneRequiredDISPCLKWithODMCombine4To1;
unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES + 1][2];
bool LinkDSCEnable;
bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
double SwathWidthCThisState[DC__NUM_DPP__MAX];
bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
unsigned int NotEnoughUrgentLatencyHiding;
unsigned int NotEnoughUrgentLatencyHidingPre;
long PTEBufferSizeInRequestsForLuma;
// Missing from VBA
long dpte_group_bytes_chroma;
unsigned int vm_group_bytes_chroma;
double dst_x_after_scaler;
double dst_y_after_scaler;
unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
/* perf locals*/
double PrefetchBandwidth[DC__NUM_DPP__MAX];
double VInitPreFillY[DC__NUM_DPP__MAX];
double VInitPreFillC[DC__NUM_DPP__MAX];
unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
unsigned int VStartup[DC__NUM_DPP__MAX];
double DSTYAfterScaler[DC__NUM_DPP__MAX];
double DSTXAfterScaler[DC__NUM_DPP__MAX];
bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
double VRatioPrefetchY[DC__NUM_DPP__MAX];
double VRatioPrefetchC[DC__NUM_DPP__MAX];
double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
double MinTTUVBlank[DC__NUM_DPP__MAX];
double BytePerPixelDETY[DC__NUM_DPP__MAX];
double BytePerPixelDETC[DC__NUM_DPP__MAX];
unsigned int SwathWidthY[DC__NUM_DPP__MAX];
unsigned int SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
double MetaRowByte[DC__NUM_DPP__MAX];
double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
double DSCCLK_calculated[DC__NUM_DPP__MAX];
unsigned int DSCDelay[DC__NUM_DPP__MAX];
unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
double DPPCLK[DC__NUM_DPP__MAX];
unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
double XFCTransferDelay[DC__NUM_DPP__MAX];
double XFCPrechargeDelay[DC__NUM_DPP__MAX];
double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
double XFCPrefetchMargin[DC__NUM_DPP__MAX];
unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
double LinesToFinishSwathTransferStutterCriticalPlane;
unsigned int BytePerPixelYCriticalPlane;
double SwathWidthYCriticalPlane;
double LinesInDETY[DC__NUM_DPP__MAX];
double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
unsigned int SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
unsigned int SwathWidthC[DC__NUM_DPP__MAX];
unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
long dummyinteger1;
long dummyinteger2;
double FinalDRAMClockChangeLatency;
double Tdmdl_vm[DC__NUM_DPP__MAX];
double Tdmdl[DC__NUM_DPP__MAX];
unsigned int ThisVStartup;
bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
double VStartupMargin;
/* Missing from VBA */
unsigned int MaximumMaxVStartupLines;
double FabricAndDRAMBandwidth;
double LinesInDETLuma;
double LinesInDETChroma;
unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
unsigned int LinesInDETC[DC__NUM_DPP__MAX];
unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1][2];
unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
double qual_row_bw[DC__NUM_DPP__MAX];
double prefetch_row_bw[DC__NUM_DPP__MAX];
double prefetch_vm_bw[DC__NUM_DPP__MAX];
double PTEGroupSize;
unsigned int PDEProcessingBufIn64KBReqs;
double MaxTotalVActiveRDBandwidth;
double MinUrgentLatencySupportUs;
double MinFullDETBufferingTime;
double AverageReadBandwidthGBytePerSecond;
bool FirstMainPlane;
unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
double HRatioChroma[DC__NUM_DPP__MAX];
double VRatioChroma[DC__NUM_DPP__MAX];
long WritebackSourceWidth[DC__NUM_DPP__MAX];
bool ModeIsSupported;
bool ODMCombine4To1Supported;
unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
bool DSCEnable[DC__NUM_DPP__MAX];
double DRAMClockChangeLatencyOverride;
double GPUVMMinPageSize;
double HostVMMinPageSize;
bool MPCCombineEnable[DC__NUM_DPP__MAX];
unsigned int HostVMMaxNonCachedPageTableLevels;
bool DynamicMetadataVMEnabled;
double WritebackInterfaceBufferSize;
double WritebackLineBufferSize;
double DCCRateLuma[DC__NUM_DPP__MAX];
double DCCRateChroma[DC__NUM_DPP__MAX];
double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
int MinVoltageLevel;
int MaxVoltageLevel;
bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
bool NumberOfHDMIFRLSupport;
unsigned int MaxNumHDMIFRLOutputs;
int AudioSampleRate[DC__NUM_DPP__MAX];
int AudioSampleLayout[DC__NUM_DPP__MAX];
};
bool CalculateMinAndMaxPrefetchMode(
enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
unsigned int *MinPrefetchMode,
unsigned int *MaxPrefetchMode);
double CalculateWriteBackDISPCLK(
enum source_format_class WritebackPixelFormat,
double PixelClock,
double WritebackHRatio,
double WritebackVRatio,
unsigned int WritebackLumaHTaps,
unsigned int WritebackLumaVTaps,
unsigned int WritebackChromaHTaps,
unsigned int WritebackChromaVTaps,
double WritebackDestinationWidth,
unsigned int HTotal,
unsigned int WritebackChromaLineBufferWidth);
#endif /* _DML2_DISPLAY_MODE_VBA_H_ */